Bond pads of semiconductor devices
A semiconductor device is provided that includes a dielectric layer, a bond pad, a passivation layer and a planar barrier. The bond pad is positioned in the dielectric layer. The passivation layer is positioned over the dielectric layer and has an opening over the bond pad. The planar barrier is positioned on the bond pad.
1. A semiconductor device comprising:
a dielectric layer;
a bond pad positioned in the dielectric layer, the bond pad having edges in the dielectric layer;
a passivation layer positioned over the dielectric layer, the passivation layer having a first opening over the bond pad; and
a planar barrier positioned on the bond pad, wherein the planar barrier peripherally overlays the edges of the bond pad and has a second opening over the bond pad, the second opening having a width at most as wide as the first opening.
2. The semiconductor device of claim 1 , wherein the planar barrier has a width ranging from 0.9 um to 1.1 um.
3. The semiconductor device of claim 1 , wherein the planar barrier has inner sidewalls on the bond pad and the inner sidewalls define the second opening.
4. The semiconductor device of claim 3 , further comprises a barrier liner covering end portions of the passivation layer at the first opening and the inner sidewalls of the planar barrier at the second opening.
5. The semiconductor device of claim 1 , further comprises a capping layer positioned adjacent to the planar barrier and between the dielectric layer and the passivation layer.
6. The semiconductor device of claim 5 , wherein the capping layer has a first thickness and the planar barrier has a second thickness, and the first thickness is substantially equal to the second thickness.
7. The semiconductor device of claim 1 , wherein the planar barrier has a thickness of at least 500 Å.
8. The semiconductor device of claim 1 , wherein the planar barrier comprises palladium, nickel, beryllium, molybdenum, or an alloy of nickel, palladium and gold.
9. The semiconductor device of claim 1 , wherein the planar barrier has a first portion overlying the edges of the bond pad and a second portion overlying the dielectric layer.
10. The semiconductor device of claim 1 , wherein the planar barrier is positioned between the dielectric layer and the passivation layer.
11. A semiconductor device comprising:
a dielectric layer;
a bond pad positioned in the dielectric layer, the bond pad having edges in the dielectric layer;
a passivation layer positioned over the dielectric layer, the passivation layer having a first opening over the bond pad; and
a planar barrier positioned on the bond pad, wherein the planar barrier peripherally overlays the edges of the bond pad and has a second opening over the bond pad, and the first opening and the second opening defining a bond pad opening.
12. The semiconductor device of claim 11 , further comprises a capping layer positioned adjacent to the planar barrier and between the dielectric layer and the passivation layer, wherein the capping layer has an upper surface, and the upper surface is substantially coplanar with the planar barrier.
13. The semiconductor device of claim 11 , wherein the bond pad comprises copper.
14. The semiconductor device of claim 11 , further comprises an external interconnect structure positioned over the bond pad through the bond pad opening.
15. The semiconductor device of claim 11 , wherein the first opening of the passivation layer is substantially coincident with the second opening of the planar barrier.
16. A method of forming a semiconductor device comprising:
forming a bond pad in a dielectric layer, the bond pad having edges in the dielectric layer;
forming a passivation layer over the dielectric layer and with a first opening over the bond pad; and
forming a planar barrier on the bond pad, wherein the planar barrier peripherally overlays the edges of the bond pad and has a second opening over the bond pad, the second opening having a width at most as wide as the first opening.
17. The method of claim 16 , wherein the forming of the planar barrier further comprises:
forming a capping layer over the dielectric layer and the bond pad;
forming trenches in the capping layer positioned at the edges of the bond pad and of the surrounding dielectric layer; and
filling the trenches with a barrier material to form the planar barrier.
18. The method of claim 16 , further comprises depositing a barrier liner over the passivation layer and covering end portions of the passivation layer at the first opening over the bond pad.