Semiconductor device having supporter pattern

1. A method of manufacturing a semiconductor device, the method comprising:

sequentially stacking a mold layer and a supporter layer on a substrate;

forming a plurality of capacitor holes, the plurality of capacitor holes passing through the mold layer and the supporter layer;

forming a plurality of lower electrodes filling the capacitor holes, the plurality of lower electrodes arranged in a first direction and a second direction which intersects with the first direction;

forming, on the supporter layer and the lower electrodes, a supporter mask pattern, the supporter mask pattern including a plurality of mask holes; and

forming a plurality of supporter holes by patterning the supporter layer using the supporter mask pattern,

wherein the plurality of lower electrodes are arranged in a honeycomb structure in which the plurality of lower electrodes are at centers and vertices of hexagons, each of the plurality of lower electrodes has a pillar shape,

wherein one of the mask holes of the supporter mask pattern exposes two of the plurality of lower electrodes and a top surface of the supporter layer,

wherein the one of the mask holes of the supporter mask pattern includes a first width in the first direction and a second width in the second direction that is substantially same as the first width,

wherein one of the plurality of supporter holes of the supporter layer exposes four of the plurality of lower electrodes, and

wherein the one of the plurality of supporter holes of the supporter layer includes a third width in the first direction and a fourth width in the second direction that is greater than the third width.

2. The method of claim 1 , wherein each of the mask holes is between four adjacent lower electrodes.

3. The method of claim 2 , wherein each of the plurality of supporter holes is formed across the four adjacent lower electrodes.

4. The method of claim 3 , wherein:

two lower electrodes, among the four adjacent lower electrodes, have first open areas, the two lower electrodes being close to a center of the support hole; and

the two remaining lower electrodes among the four adjacent lower electrodes have second open areas which are smaller than the first open areas.

5. The method of claim 2 , wherein both cross-sectional areas of upper surfaces of two lower electrodes among the four lower electrodes, which are close to a center of the supporter hole, are smaller than those of upper surfaces of the two remaining lower electrodes.

6. The method of claim 1 , wherein each of the plurality of supporter holes has an oval shape.

7. The method of claim 1 , wherein at least one among the plurality of supporter holes exposes a corresponding one of the plurality of lower electrodes.

8. The method of claim 1 , wherein each of the plurality of supporter holes has a minor axis in the first direction and a major axis in the second direction.

9. The method of claim 1 , wherein the supporter layer comprises silicon nitride.

10. The method of claim 1 , wherein:

a distance between centers of the plurality of supporter holes is 6.0 minimum lithographic feature sizes (F); and

the plurality of supporter holes are arranged in a honeycomb structure in which the plurality of supporter holes are at centers and vertices of hexagons.

11. The method of claim 1 , wherein:

the plurality of supporter holes form a plurality of columns in which a distance between centers thereof is about 5.2 F in the second direction; and

the columns adjacent to each other are disposed to be spaced apart from each other by about 4.5 F in the first direction and misaligned with each other by about 2.6 F in the second direction.

12. The method of claim 1 , wherein the plurality of supporter holes have a lattice structure in which a distance between centers thereof is 6.0 F.

13. The method of claim 1 , wherein each of the plurality of supporter holes has a major axis in a direction inclined 30° in a counterclockwise direction from an axis of the first direction.

14. The method of claim 1 , wherein each of the plurality of supporter holes has a major axis in a direction inclined 30° in a clockwise direction from an axis of the first direction.

15. A method of manufacturing a semiconductor device, the method comprising:

sequentially stacking a mold layer and a supporter layer on a substrate;

forming a plurality of capacitor holes passing through the mold layer and the supporter layer;

forming a plurality of lower electrodes filling the capacitor holes, the plurality of lower electrodes arranged in a first direction and a second direction which intersects with the first direction;

forming, on the supporter layer and the lower electrodes, a supporter mask pattern, the supporter mask pattern comprising a plurality of mask holes; and

forming a plurality of first supporter holes and a plurality of second supporter holes arranged in a direction which is different from a direction of the first supporter holes by patterning the supporter layer using the supporter mask pattern,

wherein each of the plurality of lower electrodes has a pillar shape, each of the mask holes is between four adjacent lower electrodes, and each of the mask holes has a circular shape.

16. The method of claim 15 , wherein:

each of the first supporter holes has a major axis in a direction inclined 30° from an axis of the first direction in a counterclockwise direction; and

each of the second supporter holes has a major axis in a direction inclined 30° from an axis of the first direction in a clockwise direction.

17. The method of claim 15 , wherein:

the plurality of first supporter holes form first columns arranged to be spaced apart from each other in the second direction;

the plurality of second supporter holes form second columns arranged to be spaced apart from each other in the second direction; and

the first columns and the second columns are alternately arranged.

18. The method of claim 15 , wherein each of the plurality of lower electrodes is opened by at least one among the plurality of supporter holes.

19. A method of manufacturing a semiconductor device, the method comprising:

sequentially stacking a mold layer and a supporter layer on a substrate;

forming a plurality of capacitor holes passing through the mold layer and the supporter layer;

forming a plurality of lower electrodes filling the capacitor holes, the plurality of lower electrodes arranged in a first direction and a second direction which intersects with the first direction, and the plurality of lower electrodes are arranged in a honeycomb structure in which the plurality of lower electrodes are at centers and vertices of hexagons;

forming, on the supporter layer and the lower electrodes, a supporter mask pattern, the support mask pattern comprising a plurality of mask holes; and

forming a plurality of supporter holes by patterning the supporter layer using the supporter mask pattern,

wherein each of the plurality of lower electrodes has a pillar shape and, each of the plurality of lower electrodes is exposed by at least one among the plurality of supporter holes, each of the mask holes is between four adjacent lower electrodes, each of the mask holes has a circular shape, each of the supporter holes is between the four adjacent lower electrodes, and each of the supporter holes has an oval shape.