Semiconductor structure and method of fabricating the semiconductor structure

1. A semiconductor device, comprising:

a substrate;

a fin over the substrate, wherein the fin extends along a primary direction;

a gate over the fin, the gate extends along a secondary direction orthogonal to the primary direction;

a first conductive contact over the gate, wherein a bottom surface of the first conductive contact overlaps with a top surface of the gate from a top view perspective; and

a conductive routing layer over the first conductive contact, wherein at least a portion of the fin is free from the coverage of a vertical projection of the conductive routing layer.

2. The semiconductor device of claim 1 , further comprising a conductive pattern over the fin, wherein the conductive pattern extends along the secondary direction.

3. The semiconductor device of claim 2 , further comprising a second conductive contact connecting the conductive pattern and the conductive routing layer.

4. The semiconductor device of claim 1 wherein at least a portion of the gate is free from the coverage of a vertical projection of the conductive routing layer.

5. The semiconductor device of claim 1 , wherein the fin comprises a conductive region adjacent to the gate, wherein at least a portion of the conductive region is free from the coverage of a vertical projection of the conductive routing layer.

6. The semiconductor device of claim 1 , wherein the conductive routing layer is a first metal layer over the substrate.

7. A semiconductor device, comprising:

a substrate, comprising:

an isolation region proximal to a top surface of the substrate;

a first well region under the isolation region, wherein the first well region has a first conductivity type; and

a second well region under the first well region, wherein the second well region has a second conductivity type, an interface between the first well region and the second well region is under and spaced away from the isolation region;

a fin protruding from the first well region; and

a conductive routing layer electrically coupled to the fin.

8. The semiconductor device of claim 7 , further comprising a third well region surrounding the first well region, wherein the third well region spaces between the second well region and the isolation region, the third well region has the second conductivity type.

9. The semiconductor device of claim 7 , wherein at least a portion of the interface between the first well region and the second well region is free from the coverage of a vertical projection of the conductive routing layer.

10. The semiconductor device of claim 7 , wherein the interface between the first well region and the second well region has a width wider than a width of the fin.

11. The semiconductor device of claim 7 , further comprising:

an epitaxial feature on the fin; and

a conductive contact between the epitaxial feature and the conductive routing layer.

12. The semiconductor device of claim 7 , wherein the substrate comprises a fourth well region under the second well region, wherein the fourth well region has the first conductivity type.

13. The semiconductor device of claim 7 , further comprising a gate, wherein the gate is entirely covered by the conductive routing layer from a top view perspective.

14. The semiconductor device of claim 7 , wherein the fin is entirely covered by the conductive routing layer from a top view perspective.

15. A method for fabricating a semiconductor structure, comprising:

forming a first well region in a substrate, wherein the first well region has a first conductivity type;

forming a second well region under the first well region, wherein the second well region has a second conductivity type;

forming a third well region surrounding the first well region and above the second well region, wherein the third well region has the second conductivity type;

forming a fin over the first well region; and

forming a conductive routing layer over the fin.

16. The method of claim 15 , wherein at least a portion of the first well region is free from the coverage of a vertical projection of the conductive routing layer.

17. The method of claim 15 , wherein at least a portion of an interface between the first well region and the second well region is free from the coverage of a vertical projection of the conductive routing layer.

18. The method of claim 15 , further comprising performing a plasma operation over the substrate.

19. The method of claim 15 , further comprising forming a conductive contact connecting to the fin prior to forming the conductive routing layer.

20. The method of claim 15 , further comprising forming an isolation region proximal to a top surface of the substrate.