Integrated chip including through-substrate via (TSV) and landing structure
An integrated chip including a semiconductor substrate having a first side and a second side, opposite the first side. A first transistor and a second transistor are along the first side of the semiconductor substrate. A dielectric structure including a plurality of dielectric layers is under the first side of the semiconductor substrate. A first metal line is within the dielectric structure. A second metal line is within the dielectric structure and under the first metal line. A first metal via extends between the first metal line and the second metal line. A through-substrate via (TSV) extends from the second side of the semiconductor substrate, through the semiconductor substrate between the first transistor and the second transistor, to the first metal line and the second metal line.
1 . A method for forming an integrated chip, the method comprising:
forming a first transistor and a second transistor along a first side of a semiconductor substrate;
forming a dielectric structure comprising a plurality of dielectric layers over the first side of the semiconductor substrate;
forming a first metal line within the dielectric structure;
forming a first metal via within the dielectric structure and over the first metal line;
forming a second metal line within the dielectric structure and over the first metal via, wherein the first metal line and the second metal line form a landing structure;
performing a first etching process into a second side of the semiconductor substrate, opposite the first side, to form a trench in the semiconductor substrate, the trench extending through the semiconductor substrate from the second side to the first side, wherein the trench is delimited by a pair of sidewalls of the semiconductor substrate;
performing a second etching process into the dielectric structure directly below the trench to extend the trench so the trench is further delimited by the dielectric structure, the first metal line, and the second metal line; and
forming a through-substrate via (TSV) over the second side of the semiconductor substrate, along the pair of sidewalls of the semiconductor substrate, on the first metal line, and on the second metal line.
2 . The method of claim 1 , wherein the first metal line is formed directly between a gate of the first transistor and a gate of the second transistor.
3 . The method of claim 1 , further comprising:
forming a third metal line within the dielectric structure and over the second metal line, wherein the third metal line further forms the landing structure, wherein the second etching process further extends the trench to the third metal line, and wherein the TSV is formed on the third metal line.
4 . The method of claim 1 , further comprising:
forming a guard ring structure comprising a plurality of metal gates, a plurality of metal lines, and a plurality of metal vias in the dielectric structure and collectively surrounding the landing structure and the TSV in a closed path.
5 . The method of claim 1 , further comprising:
depositing a dielectric liner layer over the second side of the semiconductor substrate, in the trench, and over the first metal line, wherein the second etching process extends through the dielectric liner layer directly over the first metal line.
6 . The method of claim 1 , wherein the first metal line is elongated in a first direction, and wherein the second metal line is elongated in a second direction, different than the first direction.
7 . The method of claim 1 , further comprising:
forming a shallow trench isolation (STI) layer along the first side of the semiconductor substrate, wherein the trench is partially delimited by sidewalls of the STI layer.
8 . A method for forming an integrated chip, the method comprising:
forming a dielectric structure comprising a plurality of dielectric layers over a first side of a semiconductor substrate;
forming a first metal line within the dielectric structure;
forming a second metal line within the dielectric structure and over the first metal line, wherein the first metal line and the second metal line form a landing structure;
etching through the semiconductor substrate from a second side of the semiconductor substrate to uncover a portion of the first metal line;
etching the dielectric structure to uncover a portion of the second metal line; and
forming a through-substrate via (TSV) over the second side of the semiconductor substrate, on the portion of the first metal line, and on the portion of the second metal line.
9 . The method of claim 8 , further comprising:
depositing a dielectric liner layer on sidewalls of the semiconductor substrate, an upper surface of the first metal line, and a sidewall of the first metal line before uncovering the portion of the second metal line; and
etching through the dielectric liner layer before uncovering the portion of the second metal line.
10 . The method of claim 8 , further comprising:
forming a shallow trench isolation (STI) layer between sidewalls of the semiconductor substrate along the first side of the semiconductor substrate, wherein the first metal line is formed on the STI layer.
11 . The method of claim 8 , wherein the first metal line is spaced from the first side of the semiconductor substrate with the dielectric structure therebetween.
12 . The method of claim 11 , further comprising:
forming a third metal line within the dielectric structure and over the second metal line, the third metal line further forming the landing structure; and
etching the dielectric structure to uncover a portion of the third metal line; and
forming the TSV on the portion of the third metal line.
13 . The method of claim 8 , wherein the first metal line comprises a first metal, and wherein the second metal line comprises a second metal different than the first metal.
14 . The method of claim 8 , further comprising:
forming a metal bump over the second side of the semiconductor substrate and on the TSV.
15 . A method for forming an integrated chip, the method comprising:
forming a first transistor and a second transistor along a first side of a semiconductor substrate and on opposite sides of a shallow trench isolation (STI) layer;
forming a dielectric structure over the first side of the semiconductor substrate;
forming a landing structure within the dielectric structure, the landing structure comprising:
a first metal line within the dielectric structure, the first metal line elongated in a first direction;
a second metal line within the dielectric structure and laterally spaced from the first metal line, the second metal line elongated in the first direction; and
a third metal line within the dielectric structure and over the first metal line and the second metal line, the third metal line elongated in a second direction different than the first direction; and
forming a through-substrate via (TSV) extending vertically through the semiconductor substrate, through the STI layer, and into the dielectric structure from a second side of the semiconductor substrate to a surface of the first metal line, a surface of the second metal line, and a surface of the third metal line.
16 . The method of claim 15 , wherein the TSV extends laterally from a sidewall of the first metal line to a sidewall of the second metal line.
17 . The method of claim 15 , wherein an upper surface of the TSV is between sidewalls of the semiconductor substrate.
18 . The method of claim 15 , wherein an upper surface of the TSV is between sidewalls of the dielectric structure.
19 . The method of claim 15 , further comprising:
forming a plurality of metal lines and a plurality of metal vias collectively surrounding the landing structure and the TSV in a closed path to form a guard ring structure around the landing structure and the TSV.
20 . The method of claim 15 , further comprising:
forming a first metal via within the dielectric structure and extending from the first metal line to the third metal line; and
forming a second metal via within the dielectric structure and extending from the second metal line to the third metal line.