IP Library Granted Patent US 11,266,027
Granted Patent B2
US 11,266,027 · App. 16/911,911 · Granted Mar 1, 2022

Single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor

Inventors: Siping Bai (Zhuhai, CN); Xianglan Wu (Zhuhai, CN); Zhijian Wang (Zhuhai, CN); Zhigang Yang (Zhuhai, CN); Jinqiang Zhang (Zhuhai, CN)
Assignee: RICHVIEW ELECTRONICS CO., LTD.
H05K3/429C23C14/48H05K1/115H05K3/105H05K3/42H05K3/422H05K3/423H05K3/427H05K3/048H05K3/06H05K3/108H05K3/421H05K3/426H05K3/4617H05K2201/0355H05K2201/096H05K2203/0565H05K2203/0769H05K2203/092H05K2203/1423
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Quick Facts
Patent No.
US 11,266,027
App. No.
16/911,911
Granted
Mar 1, 2022
Kind
B2
Abstract

A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board comprises the following steps: drilling a hole on a substrate, the hole comprising a blind hole and/or a through hole; on a surface of the substrate, forming a photoresist layer having a circuit negative image; forming a conductive seed layer on the surface of the substrate and a hole wall of the hole; removing the photoresist layer, and forming a circuit pattern on the surface of the substrate, wherein forming a conductive seed layer comprises implanting a conductive material below the surface of the substrate and below the hole wall of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.

Claims (4)

1. A multi-layer circuit board, successively constituted by metal foil, middle sticking layer, single-layer circuit board, middle sticking layer, single-layer circuit board, middle sticking layer, metal foil, wherein said multi-layer circuit board is provided with a hole, wherein a hole wall of said hole is formed with conductive seed layer, wherein partial region of said metal foil is removed to form a circuit pattern layer, wherein said conductive seed layer comprises a ion implantation layer implanted below the hole wall of said hole, and wherein said conductive seed layer further comprises a plasma deposition layer adhered above said ion implantation layer.

2. The multi-layer circuit board of claim 1 , wherein said ion implantation layer is located below one or more of the hole wall of said hole or a partial outer surface of said surface sticking layer, and wherein said ion implantation layer forms steady doping structure with said substrate.

3. The multi-layer circuit board of claim 2 , wherein said ion implantation layer is located below one or more of the hole wall of said hole or a partial outer surface of said surface sticking layer for a depth of 1-500 nm.

4. The multi-layer circuit board of claim 1 , wherein the plasma deposition layer has a thickness of 1-10000 nm.

Assignments (2)
CHANGE OF NAME Recorded Aug 6, 2025
From: RICHVIEW ELECTRONICS CO., LTD.
To: THINKTRANS ELECTRONIC MATERIALS (SHENZHEN) CO., LTD.
Reel/Frame 072361/0575 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2020
From: BAI, SIPING; WU, XIANGLAN; WANG, ZHIJIAN; YANG, ZHIGANG; ZHANG, JINQIANG
To: RICHVIEW ELECTRONICS CO., LTD.
Reel/Frame 053040/0108 →
Priority Claims (1)
CN 201510747884.1 · Nov 6, 2015 · national
Continuity (3)
Division 16382103 · Apr 11, 2019
Division 15773772
Related Publication 20200329567A1 · Oct 15, 2020