Semiconductor memory device and method for manufacturing semiconductor memory device
According to one embodiment, a semiconductor memory device includes a stacked body disposed in a first tier, the stacked body including a plurality of conductive layers stacked via an insulating layer; a first pillar that extends in the stacked body in a stacking direction of the stacked body; a first upper structure disposed in a second tier upper than the first tier; and a misalignment mark for inspecting misalignment between the first tier and the second tier, wherein the misalignment mark includes a second pillar that extends the first tier of the misalignment inspection region in the stacking direction, and a second upper structure disposed in the second tier of the misalignment inspection region and superposed on the second pillar in a top view.
1. A semiconductor memory device comprising:
a stacked body disposed in a first tier, the stacked body including a plurality of conductive layers stacked via an insulating layer;
a first pillar that extends in the stacked body in a stacking direction of the stacked body, the first pillar having a plurality of memory cells formed at respective intersections of the first pillar and at least part of the plurality of conductive layers;
a first upper structure disposed in a second tier upper than the first tier; and
a misalignment mark including a first mark disposed in the first tier of a misalignment inspection region outside the stacked body and a second mark disposed in the second tier of the misalignment inspection region and for inspecting misalignment between the first tier and the second tier,
wherein the misalignment mark further includes:
a second pillar that extends in the first tier of the misalignment inspection region in the stacking direction; and
a second upper structure disposed in the second tier of the misalignment inspection region and superposed on the second pillar in a top view.
2. The semiconductor memory device according to claim 1 ,
wherein the first upper structure is a first contact that is connected to the first pillar.
3. The semiconductor memory device according to claim 2 ,
wherein
the second pillar includes a plurality of second pillars, and
the second upper structure lies across a region that is superposed on the plurality of second pillars in a top view.
4. The semiconductor memory device according to claim 3 ,
wherein a size of a top surface of each of the second pillars is substantially equal to a size of a top surface of the first pillar, and
a size of a top surface of the second upper structure is larger than a size of a top surface of the first upper structure.
5. The semiconductor memory device according to claim 3 ,
wherein a top surface of each of the second pillars is in contact with a bottom surface of the second upper structure.
6. The semiconductor memory device according to claim 1 , further comprising:
a peripheral circuit that is disposed outside the stacked body and contributes to operation of the memory cells; and
a second contact that is connected to the peripheral circuit and extends in the first tier in the stacking direction,
wherein the first upper structure is a wiring layer that is electrically connected to the second contact.
7. The semiconductor memory device according to claim 6 ,
wherein
the second pillar includes a plurality of second pillars, and
the second upper structure is kept within a region that is superposed on one of the second pillars in a top view.
8. The semiconductor memory device according to claim 7 ,
wherein a size of a top surface of each of the second pillars is substantially equal to a size of a top surface of the first pillar, and
a size of a top surface of the second upper structure is substantially equal to a size of a top surface of the first upper structure in a width direction.
9. The semiconductor memory device according to claim 7 ,
wherein a top surface of each of the second pillars is separated apart from a bottom surface of the second upper structure.
10. The semiconductor memory device according to claim 1 ,
wherein the first mark and the second mark are arranged in a peripheral edge section of the misalignment inspection region, and
the second pillar and the second upper structure are arranged in a center section of the misalignment inspection region surrounded by the first mark and the second mark.
11. The semiconductor memory device according to claim 10 ,
wherein the second mark is not superposed on the first mark in a top view.
12. The semiconductor memory device according to claim 1 ,
wherein the first pillar includes a plurality of first pillars and the second pillar includes a plurality of second pillars, and
at least a part of the plurality of the first pillars and at least a part of the plurality of the second pillars have a portion that is inclined relative to the stacking direction.