Semiconductor memory device
A memory plane region includes a first structure and a second structure having conductive layers, and includes a first memory region to a third memory region, a first region between the first memory region and the second memory region, and a second region between the second memory region and the third memory region. The first structure comprises first via contact electrodes in the first region. The second structure comprises second via contact electrodes in the second region. The first via contact electrodes are electrically connected to transistors provided at positions where the first structure and the first region overlap, and where the second structure and the first region overlap. The second via contact electrodes are electrically connected to transistors provided at positions where the first structure and the second region overlap, and where the second structure and the second region overlap.
1 . A semiconductor memory device comprising:
a first structure having a plurality of first conductive layers that are continuous in a first direction and are laminated in a laminating direction which intersects the first direction; and
a second structure having a plurality of second conductive layers that are continuous in the first direction, are laminated in the laminating direction, are aligned in a second direction which intersects the first direction and the laminating direction with respect to the first conductive layers, and are electrically independent from the first conductive layers, wherein
a memory plane region, which includes the first structure and the second structure, includes:
a first memory region, a second memory region, and a third memory region which are aligned in the first direction and each include: a plurality of semiconductor columns that extend in the laminating direction; and a plurality of charge accumulating films;
a first region between the first memory region and the second memory region; and
a second region between the second memory region and the third memory region,
a plurality of first transistors and a plurality of third transistors are provided in an opposite direction to the laminating direction with respect to the first structure,
a plurality of second transistors and a plurality of fourth transistors are provided in an opposite direction to the laminating direction with respect to the second structure,
the second memory region is provided between the first memory region and the third memory region,
the first structure further comprises a plurality of first via contact electrodes that are provided in the first region, extend in the laminating direction, and are connected to at least a part of the plurality of first conductive layers,
the second structure further comprises a plurality of second via contact electrodes that are provided in the second region, extend in the laminating direction, and are connected to at least a part of the plurality of second conductive layers,
a part of the plurality of first via contact electrodes are electrically connected to at least a part of the plurality of first transistors provided at a position where the first structure and the first region overlap, looking from the laminating direction,
another part of the plurality of first via contact electrodes are electrically connected to at least a part of the plurality of second transistors provided at a position where the second structure and the first region overlap, looking from the laminating direction,
a part of the plurality of second via contact electrodes are electrically connected to at least a part of the plurality of third transistors provided at a position where the first structure and the second region overlap, looking from the laminating direction, and
another part of the plurality of second via contact electrodes are electrically connected to at least a part of the plurality of fourth transistors provided at a position where the second structure and the second region overlap, looking from the laminating direction.
2 . The semiconductor memory device according to claim 1 , wherein
the plurality of semiconductor columns includes a first semiconductor column and a second semiconductor column, and
the plurality of charge accumulating films includes a first charge accumulating film and a second charge accumulating film, wherein
the first semiconductor column faces at least one of the plurality of the first conductive layers,
the second semiconductor column faces at least one of the plurality of the second conductive layers,
the first charge accumulating film is provided between at least one of the plurality of first conductive layers and the first semiconductor column, and
the second charge accumulating film is provided between at least one of the plurality of second conductive layers and the second semiconductor column.
3 . The semiconductor memory device according to claim 1 , wherein
a length in the first direction of the first memory region is shorter than a length in the first direction of the second memory region, and
a length in the first direction of the third memory region is shorter than a length in the first direction of the second memory region.
4 . The semiconductor memory device according to claim 1 , wherein
the other part of the plurality of first transistors is provided at a position where the first structure and the first memory region or second memory region overlap, looking from the laminating direction,
the other part of the plurality of second transistors is provided at a position where the second structure and the first memory region or second memory region overlap, looking from the laminating direction,
the other part of the plurality of third transistors is provided at a position where the first structure and the second memory region or third memory region overlap, looking from the laminating direction, and
the other part of the plurality of fourth transistors is provided at a position where the second structure and the second memory region or third memory region overlap, looking from the laminating direction.
5 . The semiconductor memory device according to claim 1 , further comprising
a sense amplifier which includes a plurality of fifth transistors provided at at least either of a position where the first structure and second memory region overlap or a position where the second structure and second memory region overlap, in an opposite direction to the laminating direction with respect to the first structure and the second structure,
wherein the memory plane region further comprises a wiring layer which is provided between the plurality of fifth transistors and the first conductive layers and second conductive layers,
the wiring layer comprises:
a first wiring which extends in the first direction and electrically connects at least a part of the plurality of semiconductor columns in the first memory region and a part of the plurality of fifth transistors; and
a second wiring which extends in the first direction and electrically connects at least a part of the plurality of semiconductor columns in the second memory region and another part of the plurality of fifth transistors,
the first wiring extends over the first memory region, the first region, and the second memory region, looking from the laminating direction, and
the second wiring is provided at a position overlapping the second memory region, looking from the laminating direction.
6 . The semiconductor memory device according to claim 1 , wherein
a length in the first direction of the first memory region is longer than a length in the first direction of the second memory region, and
a length in the first direction of the third memory region is longer than a length in the first direction of the second memory region.
7 . The semiconductor memory device according to claim 1 , further comprising
a sense amplifier which includes a plurality of sixth transistors provided at at least either of a position where the first structure and first memory region overlap or a position where the second structure and first memory region overlap, in an opposite direction to the laminating direction with respect to the first structure and the second structure,
wherein the memory plane region further comprises a wiring layer which is provided at least either between the plurality of sixth transistors and the first conductive layers or between the plurality of sixth transistors and the second conductive layers,
the wiring layer comprises:
a third wiring which extends in the first direction and electrically connects at least a part of the plurality of semiconductor columns in the first memory region and a part of the plurality of sixth transistors; and
a fourth wiring which extends in the first direction and electrically connects at least a part of the plurality of semiconductor columns in the second memory region and another part of the plurality of sixth transistors,
the third wiring is provided at a position overlapping the first memory region, looking from the laminating direction, and
the fourth wiring extends over the first memory region, the first region, and the second memory region, looking from the laminating direction.
8 . The semiconductor memory device according to claim 1 , wherein
the memory plane region comprises a first hookup region and a second hookup region that are aligned in the first direction,
the second memory region is provided between the first hookup region and the second hookup region, and
the first region is one of the first hookup region and the second hookup region.
9 . The semiconductor memory device according to claim 8 , wherein
the memory plane region further comprises a third hookup region and a fourth hookup region that are aligned in the first direction,
the second hookup region and the third hookup region are adjacent to each other, and
the second region is one of the third hookup region and the fourth hookup region.
10 . The semiconductor memory device according to claim 1 , wherein
the first structure further comprises a plurality of third via contact electrodes that extend in the laminating direction and are connected to another part of the plurality of first conductive layers,
the second memory region is provided between at least a part of the plurality of first via contact electrodes and at least a part of the plurality of third via contact electrodes, and
each of the plurality of first conductive layers is connected to any of the plurality of first via contact electrodes or any of the plurality of third via contact electrodes.
11 . The semiconductor memory device according to claim 1 , wherein
the first structure further comprises:
a third conductive layer and a fourth conductive layer that are provided in an opposite direction to the laminating direction with respect to the plurality of first conductive layers, and are aligned in the second direction, in at least the first memory region;
a fifth conductive layer and a sixth conductive layer that are provided in an opposite direction to the laminating direction with respect to the plurality of first conductive layers, and are aligned in the second direction, in at least the second memory region;
a seventh conductive layer and an eighth conductive layer that are provided in an opposite direction to the laminating direction with respect to the plurality of first conductive layers, and are aligned in the second direction, in at least the third memory region; and
a fourth via contact electrode, a fifth via contact electrode, a sixth via contact electrode, a seventh via contact electrode, an eighth via contact electrode, and a ninth via contact electrode that extend in the laminating direction and are respectively connected to the third conductive layer, the fourth conductive layer, the fifth conductive layer, the sixth conductive layer, the seventh conductive layer, and the eighth conductive layer,
the fourth via contact electrode and the fifth via contact electrode are provided in the first region,
the sixth via contact electrode and the seventh via contact electrode are provided in the first region or the second region, and
the eighth via contact electrode and the ninth via contact electrode are provided in the second region.
12 . The semiconductor memory device according to claim 1 , wherein
the second structure further comprises a plurality of columnar bodies at a position overlapping the first region,
the first region comprises:
a third region provided on one side in the first direction in the position where the first structure and the first region overlap;
a fourth region provided on another side in the first direction in the position where the first structure and the first region overlap;
a fifth region aligned in the second direction with the third region in the position where the second structure and the first region overlap; and
a sixth region aligned in the second direction with the fourth region in the position where the second structure and the first region overlap,
lengths in the laminating direction of the plurality of first via contact electrodes provided in the third region are shorter than lengths in the laminating direction of the plurality of first via contact electrodes provided in the fourth region, and
lengths in the laminating direction of the plurality of columnar bodies provided in the fifth region are longer than lengths in the laminating direction of the plurality of columnar bodies provided in the sixth region.
13 . The semiconductor memory device according to claim 12 , wherein
lengths in the laminating direction of the plurality of first via contact electrodes provided in the third region are shorter than lengths in the laminating direction of the plurality of columnar bodies provided in the fifth region, and
lengths in the laminating direction of the plurality of first via contact electrodes provided in the fourth region are longer than lengths in the laminating direction of the plurality of columnar bodies provided in the sixth region.