Techniques to improve current regulator capability to protect the secured circuit from power side channel attack
This disclosure relates to current flattening circuits for an electrical load. The current flattening circuits incorporate randomize various parameters to add noise onto the supply current. This added noise may act to reduce the signal to noise ratio in the supply current, increasing the difficulty of identifying a computational artifact signal from power rail noise.
1. A current flattening circuit for an electrical load, comprising:
a constant current source coupled between the load and a power supply;
a first randomizer coupled to perturb an output of the constant current source; and
a controlled current shunt configured to respond to a load voltage to generate a shunt current for the load.
2. The current flattening circuit of claim 1 , wherein the constant current source comprises a bandgap voltage source coupled to drive one or more gates of one or more stacked transistors.
3. The current flattening circuit of claim 1 , wherein the first randomizer comprises a digital to analog converter.
4. The current flattening circuit of claim 1 , wherein the controlled current shunt comprises a shunt transistor.
5. The current flattening circuit of claim 4 , the shunt transistor configured to receive at its gate a voltage proportional to a comparison of a reference voltage and the load voltage.
6. The current flattening circuit of claim 1 , further comprising:
a shunt transistor coupled to a load voltage node;
a differential amplifier coupled to drive a gate of the shunt transistor;
the differential amplifier comprising an input terminal coupled to a reference voltage source; and
a second randomizer coupled to perturb a reference voltage from the reference voltage source.
7. The current flattening circuit of claim 6 , wherein the reference voltage source is a bandgap voltage source.
8. The current flattening circuit of claim 6 , wherein the second randomizer comprises a digital to analog converter.
9. A current flattening circuit comprising:
a comparator;
a current shunt coupled in parallel with a load;
a reference voltage source coupled to an input of the comparator;
a first randomizer configured to perturb an output of the reference voltage source; and
the comparator configured to control the current shunt.
10. The current flattening circuit of claim 9 , further comprising:
a constant current source interposed between a power supply and the load.
11. The current flattening circuit of claim 10 , wherein the constant current source comprises at least one PMOS transistor configured in series between the power supply and the load.
12. The current flattening circuit of claim 9 , wherein the reference voltage source is a bandgap voltage source and the first randomizer is configured to randomly perturb a bandgap voltage output by the bandgap voltage source.
13. The current flattening circuit of claim 9 , wherein the first randomizer comprises a digital to analog converter configured to receive the output of the reference voltage source and a random value.
14. The current flattening circuit of claim 10 , further comprising:
a second randomizer configured to perturb the constant current source.
15. The current flattening circuit of claim 14 , wherein the second randomizer is configured to generate a randomly perturbed bandgap voltage.
16. The current flattening circuit of claim 9 , wherein the current shunt is an NMOS transistor.
17. A current flattening circuit comprising:
at least one transistor interposed between a power supply and a load;
a current shunt coupled to a load voltage node between the at least one transistor and the load;
a comparator coupled to the load voltage node and to a reference voltage, the comparator coupled to control the current shunt; and
a randomizer coupled to perturb a clock driving the load.
18. The current flattening circuit of claim 17 the randomizer comprising:
a clock generator configured to generate a clock signal at a frequency higher than a clock frequency at which the load operates; and
a clock edge blocking circuit coupled to the clock generator and configured with a randomized blocking signal.
19. A circuit comprising:
a load path from a power supply through a load to a ground;
a shunt path across the load path;
a constant current source disposed on a segment of the load path between the power supply and the load; and
a randomizer circuit to introduce randomized current fluctuations into the load path.
20. The circuit of claim 19 , the randomizer circuit coupled to introduce the fluctuations into the load path via an input of the constant current source.
21. The circuit of claim 19 , the randomizer circuit coupled to introduce the fluctuations into the segment of the load path between the power supply and the load by introducing the fluctuations into a circuit in the shunt path.
22. The circuit of claim 19 , the randomizer circuit coupled to introduce the fluctuations into the load path via the load.
23. The circuit of claim 22 , wherein the fluctuations are introduced via a clock signal to the load.
24. The circuit of claim 19 , wherein the constant current source comprises a bandgap voltage source coupled to drive one or more gates of one or more stacked transistors.
25. The circuit of claim 19 , wherein the randomizer circuit comprises a digital to analog converter.
26. The circuit of claim 19 , the shunt path comprising a transistor configured to receive at its gate a voltage proportional to a comparison of a reference voltage and a load voltage, where the load voltage is a voltage at a junction node of the shunt path and the load path.
27. The circuit of claim 26 , the reference voltage provided from a bandgap voltage source.