Layout parasitics and device parameter prediction using graph neural networks
A graph neural network to predict net parasitics and device parameters by transforming circuit schematics into heterogeneous graphs and performing predictions on the graphs. The system may achieve an improved prediction rate and reduce simulation errors.
1. A system comprising:
at least one graph neural network;
graph generation logic configured to transform a circuit netlist into a graph; and embedding logic configured to generate a node embedding for the graph in the at least one graph neural network, the node embedding formed by concatenating previously generated node embeddings with aggregated neighbor embeddings, the node embedding configured with different edge types of the graph grouped independently for processing by different attention layers of the at least one graph neural network, wherein the at least one graph neural network is configured to transform edges of the graph into parasitic resistance predictions for the circuit netlist.
2. The system of claim 1 , further comprising:
a plurality of graph neural networks each configured to transform the node embeddings into a different range of parasitic prediction values for the circuit netlist.
3. The system of claim 2 , wherein each of the plurality of graph neural networks are configured to form a node embedding for a next network layer by applying weights of the next network layer to a unified vector generated by combining outputs of the attention layers.
4. The system of claim 2 , wherein the parasitic prediction values are capacitive parasitic predictions.
5. The system of claim 3 , wherein the ranges have a common base level.
6. The system of claim 1 , wherein the at least one graph neural network is configured to transform the graph into parasitic predictions and device parameter predictions for the circuit netlist.
7. The system of claim 6 , further comprising:
a circuit simulator configured to receive the parasitic predictions and the device parameter predictions from the at least one graph neural network.
8. The system of claim 1 , wherein the graph comprises:
device nodes and net nodes; and
a plurality of heterogeneous edge types between the device nodes and the net nodes.
9. The system of claim 8 , wherein the heterogeneous edge types comprise net to transistor drain edges, net to transistor gate edges, transistor drain to net edges, and transistor gate to net edges.
10. The system of claim 8 , wherein:
the graph excludes edges between the device nodes and power rails and between the device nodes and ground rails.
11. The system of claim 1 , wherein:
the embedding logic is configured to sum vectors for groups of multiple edges of the graph into individually weighted vectors;
the at least one graph neural network is configured to:
apply a self-attention layer separately to the individually weighted vectors for each group; and
combine outputs of the self-attention layers for groups representing a same edge type into an output vector.
12. A circuit simulator comprising:
a graphics processing unit;
at least one graph neural network;
a non-transitory machine-readable media comprising instructions that, when applied to the graphics processing unit: generate a node embedding in a graph neural network for a graph representing a circuit, the node embedding formed by concatenating previously generated node embeddings with aggregated neighbor embeddings, the node embeddings configured with different edge types of the graph grouped independently for processing by different attention layers of the graph neural network; and operate the at least one graph neural network to transform edges of the graph into parasitic predictions for the circuit, wherein the instructions, when applied to the graphics processing unit, operate the at least one graph neural network to transform edges of the graph into parasitic resistance predictions for the circuit.
13. The circuit simulator of claim 12 , wherein the instructions, when applied to the graphics processing unit, operate a plurality of graph neural networks to transform the node embeddings into a plurality of different ranges of parasitic prediction values for the circuit.
14. The circuit simulator of claim 13 , wherein the parasitic prediction values are capacitive parasitic predictions.
15. The circuit simulator of claim 13 , wherein the ranges have a common base level.
16. The circuit simulator of claim 12 , wherein the instructions, when applied to the graphics processing unit, operate the at last one graph neural network to transform the graph into parasitic predictions and device parameter predictions for the circuit.
17. The circuit simulator of claim 12 , wherein the graph comprises:
transistor device nodes and net nodes; and
a plurality of heterogeneous edge types between the transistor device nodes and the net nodes.
18. The circuit simulator of claim 17 , wherein the heterogeneous edge types comprise net to transistor drain edges, net to transistor gate edges, transistor drain to net edges, and transistor gate to net edges.