IP Library › Granted Patent US 11,289,426
Granted Patent B2
US 11,289,426 · App. 16/009,208 · Granted Mar 29, 2022

Semiconductor package and manufacturing method thereof

Inventors: Yung-Chi Chu (Kaohsiung, TW); Hung-Jui Kuo (Hsinchu, TW); Jhih-Yu Wang (New Taipei, TW); Yu-Hsiang Hu (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L23/5389H01L21/4853H01L21/4857H01L21/4864H01L21/565H01L21/568H01L21/6835H01L23/3121H01L23/5383H01L23/5386H01L23/562H01L23/564H01L23/585H01L24/19H01L24/20H01L2221/68372H01L2224/214
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,289,426
App. No.
16/009,208
Granted
Mar 29, 2022
Kind
B2
Abstract

A package includes a die and a redistribution structure. The die has an active surface and is wrapped around by an encapsulant. The redistribution structure disposed on the active surface of the die and located above the encapsulant, wherein the redistribution structure comprises a conductive via connected with the die, a routing pattern located above and connected with the conductive via, and a seal ring structure, the seal ring structure includes a first seal ring element and a second seal ring element located above and connected with the first seal ring element, wherein the second seal ring element includes a seed layer sandwiched between the first seal ring element and the second seal ring element, and a top surface of the first seal ring element is substantially coplanar with a top surface of the conductive via.

Claims (8)

1. A package, comprising:

a die, having an active surface and wrapped around by an encapsulant; and

a redistribution structure disposed on the active surface of the die and located above the encapsulant, wherein the redistribution structure comprises a conductive via connected with the die, a routing layer located above and connected with the conductive via, and a seal ring structure, the seal ring structure includes a first seal ring element and a second seal ring element located above and connected with the first seal ring element, wherein the second seal ring element includes a seed layer sandwiched between the first seal ring element and the second seal ring element, and a top surface of the first seal ring element is substantially coplanar with a top surface of the conductive via.

2. The package according to claim 1 , wherein the redistribution structure further comprises a dielectric layer wrapping around the conductive via and the first seal ring element, a top surface of the dielectric layer is substantially coplanar with the top surfaces of the conductive via and the first seal ring element, and the dielectric layer has a thickness substantially equivalent to those of the conductive via and the first seal ring element.

3. The package according to claim 1 , wherein the redistribution structure further comprises a dielectric layer wrapping around the conductive via and the first seal ring element, a top surface of the dielectric layer is lower than the top surfaces of the conductive via and the first seal ring element.

4. The package according to claim 3 , wherein a portion of the seed layer located directly on the top surface of the first seal ring element is higher than the rest of the seed layer located directly on the dielectric layer.

5. The package according to claim 1 , wherein the redistribution structure further comprises a dielectric layer wrapping around the conductive via and the first seal ring element, a top surface of the dielectric layer is higher than the top surfaces of the conductive via and the first seal ring element.

6. The package according to claim 5 , wherein a portion of the seed layer located directly on the top surface of the first seal ring element is lower than the rest of the seed layer located directly on the dielectric layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 31, 2018
From: CHU, YUNG-CHI; KUO, HUNG-JUI; WANG, JHIH-YU; HU, YU-HSIANG
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 046519/0918 →
Continuity (1)
Related Publication 20190385951A1 · Dec 19, 2019
Cited By (1)
US 12,205,903