Microelectronic package with substrate-integrated components
Embodiments may relate to a microelectronic package or a die thereof which includes a die, logic, or subsystem coupled with a face of the substrate. An inductor may be positioned in the substrate. Electromagnetic interference (EMI) shield elements may be positioned within the substrate and surrounding the inductor. Other embodiments may be described or claimed.
1. A microelectronic package, comprising:
a package substrate;
a die coupled with a face of the package substrate;
overmold material at least partially surrounding the die, wherein the overmold material comprises a conductive through-mold via (TMV) proximate to the die;
a first inductor and a second inductor positioned in the package substrate and within a die shadow of the die; and
electromagnetic interference (EMI) shield elements positioned within the package substrate and surrounding the first inductor and the second inductor, wherein:
the package substrate comprises a first redistribution layer having a first thickness and a second redistribution layer having a second thickness, the second thickness being less than the first thickness,
the first inductor is in the first redistribution layer,
the second inductor is in the second redistribution layer, and
the second inductor has a lower Q-factor than the first inductor.
2. The microelectronic package of claim 1 , wherein at least one of the first inductor and the second inductor includes a metal element positioned in two layers of the package substrate.
3. The microelectronic package of claim 1 , wherein at least one of the first inductor and the second inductor includes a conductive element in a first layer of the package substrate, a conductive element in a second layer of the package substrate, and a conductive element in a third layer of the package substrate, and wherein the conductive elements of the first layer and the second layer are electronically coupled by a trench via.
4. The microelectronic package of claim 1 , wherein the EMI shield elements include a through-substrate via (TSV) within the package substrate.
5. The microelectronic package of claim 1 , wherein the EMI shield elements further surround the die.
6. The microelectronic package of claim 1 , wherein the die is a power amplifier (PA) or an acoustic wave resonator (AWR).
7. The microelectronic package of claim 1 , wherein:
the package substrate includes a plurality of layers,
the plurality of layers includes a first subset of layers comprising the first redistribution layer, wherein respective layers of the first subset of layers has a first z-height, and
the plurality of layers includes a second subset of layers comprising the second redistribution layer, wherein respective layers of the second subset of layers has a second z-height.
8. The microelectronic package of claim 1 , wherein the microelectronic package has a height of less than 300 micrometers.
9. The microelectronic package of claim 1 , wherein the inductor is a multi-loop inductor.
10. The microelectronic package of claim 1 , wherein the microelectronic package is a RF front-end module (FEM).
11. The microelectronic package of claim 1 , further comprising an EMI shield layer above the overmold material over at least a portion of the die.
12. An electrical device, comprising:
a processing device; and
a communication chip,
wherein at least one of the processing device and the communication chip includes a microelectronic package that includes:
a package substrate comprising a first redistribution layer and a second redistribution layer, the second redistribution layer being thinner than the first redistribution layer,
a die coupled with a face of the package substrate,
overmold material at least partially surrounding the die, and comprising a conductive TMV proximate to the die,
a first inductor and a second inductor positioned in the first redistribution layer and the second redistribution layer respectively of the package substrate and within a die shadow of the die, and
electromagnetic interference (EMI) shield elements positioned within the package substrate and surrounding the inductor.
13. The electrical device of claim 12 , wherein at least one of the first inductor and the second inductor includes a metal element positioned in two layers of the package substrate.