Die stacking package architecture for high-speed input/output with through-dielectric vias
Embodiments of a microelectronic assembly comprise a package substrate, a first integrated circuit (IC) die, a second IC die between the first IC die and the package substrate, a dielectric material between the first IC die and the package substrate, and a plurality of vias through the dielectric material, the vias coupling the first IC die and the package substrate. The microelectronic assembly is in a space defined by three mutually orthogonal axes, a first axis, a second axis and a third axis; the package substrate, the first IC die and the second IC die are mutually parallel in first planes defined by the first axis and the third axis; the vias are in one or more second planes defined by the second axis and the third axis; and the vias are inclined at an angle not equal to ninety degrees around the first axis.
1 . A microelectronic assembly, comprising:
a package substrate;
a first integrated circuit (IC) die;
a second IC die between the first IC die and the package substrate;
a dielectric material at least between the first IC die and the package substrate; and
a plurality of vias through the dielectric material, the vias coupling the first IC die and the package substrate,
wherein:
the microelectronic assembly is in a space defined by three mutually orthogonal axes, namely a first axis, a second axis, and a third axis,
the package substrate, the first IC die and the second IC die are mutually parallel in first planes defined by the first axis and the third axis,
the vias are in one or more second planes defined by the second axis and the third axis, and
the vias are inclined at an angle not equal to ninety degrees around the first axis.
2 . The microelectronic assembly of claim 1 , wherein the second IC die comprises a stack of the second IC dies arranged in a plurality of layers, adjacent layers being coupled by first-level interconnects (FLIs).
3 . The microelectronic assembly of claim 2 , wherein:
the vias in the plurality of vias are first vias,
a particular second IC die in the stack is a third IC die,
the third IC die in the stack is not adjacent to the first IC die,
the first IC die is coupled to the third IC die by a plurality of second vias,
the second vias are in the one or more second planes defined by the second axis and the third axis, and
the second vias are inclined at angles not equal to ninety degrees around the first axis.
4 . The microelectronic assembly of claim 3 , wherein:
the first IC die comprises a plurality of digital logic circuits; and
the plurality of second vias couple at least a subset of the plurality of digital logic circuits with one or more of the second IC dies.
5 . The microelectronic assembly of claim 3 , wherein:
another IC die in the stack between the first IC die and the package substrate is a fourth IC die,
the fourth IC die not adjacent to the third IC die,
the fourth IC die is coupled to the third IC die by one or more third vias,
the third vias are in the one or more second planes defined by the second axis and the third axis, and
the third vias are inclined at angles not equal to ninety degrees around the first axis.
6 . The microelectronic assembly of claim 2 , wherein:
the vias in the plurality of vias are first vias,
one or more IC dies in the stack of second IC dies are third IC dies,
the third IC dies are not adjacent to the package substrate,
the third IC dies are coupled to the package substrate by a plurality of second vias,
the second vias are in the one or more second planes defined by the second axis and the third axis, and
the second vias are inclined at angles not equal to ninety degrees around the first axis.
7 . The microelectronic assembly of claim 6 , wherein:
a particular one of the second IC die in the stack is a fourth IC die,
one of the third IC dies is between the first IC die and the fourth IC die,
the first IC die overhangs beyond an edge of the one of the third IC dies by a first overhang region,
at least a subset of the plurality of first vias is in the first overhang region,
the one of the third IC dies overhangs beyond an edge of the fourth IC die by a second overhang region, and
at least a subset of the plurality of second vias is in the second overhang region.
8 . The microelectronic assembly of claim 1 , wherein the vias in the plurality of vias are arranged in parallel rows, each row being in one of the second planes, and the microelectronic assembly further comprises metal plates between any two adjacent rows.
9 . The microelectronic assembly of claim 1 , wherein the dielectric material comprises an organic material selected from at least one of mold compound, underfill material, and polyimide.
10 . An IC package, comprising:
a package substrate;
a first IC die coupled to the package substrate;
a second IC die on a side of the first IC die opposite to the package substrate;
a third IC die coupled to the second IC die on a side of the second IC die opposite to the first IC die;
a dielectric material surrounding at least the first IC die and the second IC die; and
a via through the dielectric material, the via coupling the third IC die and the package substrate,
wherein:
at least one surface each of the third IC die and the package substrate are mutually parallel, and
the via is inclined at an angle not equal to ninety degrees with respect to the third IC die or the package substrate in a plane orthogonal to the at least one surface.
11 . The IC package of claim 10 , wherein the via is a first via, and the IC package further comprises a second via through the dielectric material, wherein:
the second via couples the third IC die and the package substrate, and
the second via is not parallel to the first via.
12 . The IC package of claim 11 , further comprising a metal plate adjacent to the first via and the second via, wherein:
the metal plate extends between the third IC die and the package substrate, and
the metal plate is parallel to the first via and the second via.
13 . The IC package of claim 10 , wherein:
the via is a first via,
the IC package further comprises a second via through the dielectric material,
the second via couples the second IC die and the package substrate,
the second IC die and the package substrate are substantially parallel to each other, and
the second via is inclined at angles not equal to ninety degrees with respect to the third IC die or the package substrate in a plane orthogonal to the at least one surface.
14 . The IC package of claim 13 , further comprising a first digital logic circuit and a second digital logic circuit, wherein the third IC die and the second IC die are coupled by wire-bonds.
15 . The IC package of claim 10 , wherein:
the via is a first via,
the IC package further comprises a second via through the dielectric material,
the second via couples the third IC die and the first IC die,
the third IC die and the first IC die are substantially parallel to each other, and
the second via is inclined at angles not equal to ninety degrees with respect to the third IC die or the first IC die in a plane orthogonal to the at least one surface.
16 . The IC package of claim 15 , further comprising:
a plurality of digital logic circuits in the third IC die;
a fourth IC die between the second IC die and the first IC die; and
a third via through the dielectric material,
wherein:
the third via couples the second IC die and the first IC die,
the first IC die and the second IC die are substantially parallel to each other, and
the third via is inclined at angles not equal to ninety degrees with respect to the first IC die or the second IC die in a plane orthogonal to the at least one surface.
17 . The IC package of claim 10 , wherein the dielectric material comprises at least one of: mold compound and underfill material.
18 . The microelectronic assembly of claim 1 , wherein the first IC die and the second IC die each comprise a substrate, a metallization stack, and an active region between the substrate and the metallization stack.
19 . The microelectronic assembly of claim 18 , wherein the metallization stack of the first IC die is adjacent to and in contact with one of the substrate of the first IC and the metallization stack of the second IC.
20 . The microelectronic assembly of claim 8 , wherein vias in any one row are mutually parallel to each other.