IP Library Granted Patent US 11,320,701
Granted Patent B2
US 11,320,701 · App. 17/098,685 · Granted May 3, 2022

Active matrix substrate and a liquid crystal display

Inventor: Takahiro Mori (Sakai, JP)
Assignee: SHARP KABUSHIKI KAISHA
G02F1/1339G02F1/1345G02F1/1368G02F1/133345G02F1/133512G02F1/136213G09G3/3677G11C19/28G11C19/287G09G2300/0408G09G2310/0286
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Quick Facts
Patent No.
US 11,320,701
App. No.
17/098,685
Granted
May 3, 2022
Kind
B2
Abstract

The present invention provides a liquid crystal display that can reduce occurrence of quality problems and improve adhesive strength between substrates. The present invention is a liquid crystal display including a first substrate, a second substrate, and a seal. The first substrate includes a shift register monolithically formed on an insulating substrate, a plurality of bus lines, a first end, and a display region. The shift register includes a plurality of multistage-connected unit circuits and wiring connected to the plurality of unit circuits, and is arranged in a region between the first end and the display region. At least one of the unit circuits includes a clock terminal, an output terminal, an output transistor, a second transistor, and a bootstrap capacitor. The output transistor and the bootstrap capacitor are arranged in a region between the first end and one of the wiring and the second transistor.

Claims (29)

1. An active matrix substrate comprising:

an insulating substrate, a shift register monolithically formed on the insulating substrate, a plurality of gate bus lines, a first end of the insulating substrate, and a display region,

the shift register includes a plurality of unit circuits that are multistage-connected and wiring connected to the plurality of unit circuits,

the shift register being arranged in a region between the first end and the display region, at least one of the plurality of unit circuits includes:

a clock terminal into which a clock signal is input,

an output terminal connected to a corresponding gate bus line, the output terminal outputting an output signal,

a first transistor with one of a source and a drain being connected to the clock terminal and the other of the source and the drain being connected to the output terminal,

a second transistor electrically connected to a gate of the first transistor; and

a capacitor with a first terminal being directly connected to a gate of said first transistor and a second terminal being directly connected to the output terminal, and

the wiring connected to the plurality of unit circuits includes at least one of a first wiring for supplying a low-level potential to the unit circuit and a second wiring for transmitting the clock signal to the unit circuit,

the capacitor is arranged at a position different from a position of the first transistor and adjacent to the first transistor in a plan view,

the first transistor and the capacitor are arranged in a region between the first end and the second transistor,

the wiring connected to the plurality of unit circuits is arranged in a region between one of the first transistor and the capacitor and the first end,

the second transistor is arranged in a region between one of the first transistor and the capacitor and the display region.

2. The active matrix substrate according to claim 1 , wherein the first transistor, the second transistor, and the capacitor are arranged along a direction where the plurality of gate bus lines extend.

3. The active matrix substrate according to claim 1 , wherein at least one of the plurality of unit circuits includes a plurality of the second transistor.

4. The active matrix substrate according to claim 1 , wherein at least a portion of the capacitor is arranged in a region between the first transistor and the second transistor.

5. The active matrix substrate according to claim 4 ,

wherein the wiring is arranged in a region between the first transistor and the first end, and

the second transistor is arranged in a region between the capacitor and the display region.

6. The active matrix substrate according to claim 1 , wherein at least a portion of the capacitor is arranged in a region between the first transistor and the wiring connected to the plurality of unit circuits.

7. The active matrix substrate according to claim 6 ,

wherein the wiring is arranged in a region between the capacitor and the first end, and

the second transistor is arranged in a region between the first transistor and the display region.

8. A liquid crystal display comprising:

the active matrix substrate according to claim 1 ,

a second substrate facing the active matrix substrate, and

a seal provided between the active matrix substrate and the second substrate.

9. The liquid crystal display according to claim 8 , wherein the second substrate includes a light shielding portion that faces the shift register.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 16, 2020
From: MORI, TAKAHIRO
To: SHARP KABUSHIKI KAISHA
Reel/Frame 054375/0312 →
Priority Claims (1)
JP 2012-112771 · May 16, 2012 · national
Continuity (2)
Continuation 14397897
Related Publication 20210072575A1 · Mar 11, 2021
Cited By (1)
US 12,475,836