IP Library › Granted Patent US 11,322,478
Granted Patent B2
US 11,322,478 · App. 16/855,110 · Granted May 3, 2022

Semiconductor device and semiconductor device array

Inventors: Takaharu Yamano (Nagano, JP); Yoshihiro Ihara (Nagano, JP)
Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
H01L25/0655H01L23/3121H01L24/20
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Quick Facts
Patent No.
US 11,322,478
App. No.
16/855,110
Granted
May 3, 2022
Kind
B2
Abstract

A semiconductor device includes a wiring substrate and multiple semiconductor chips mounted on the wiring substrate by flip chip bonding with a resin being interposed between the wiring substrate and the semiconductor chips. The wiring substrate includes a chip mounting region in which the semiconductor chips are arranged in a matrix, and a resin injection region protruding from an end of the chip mounting region. The outer edge of the wiring substrate in the chip mounting region is positioned inward of the outer edge of the semiconductor chips arranged in the matrix. The outer edge of the wiring substrate in the resin injection region protrudes outward of the outer edge of the semiconductor chips arranged in the matrix.

Claims (27)

1. A semiconductor device comprising:

a wiring substrate; and

a plurality of semiconductor chips mounted on the wiring substrate by flip chip bonding with a resin being interposed between the wiring substrate and the semiconductor chips,

wherein the wiring substrate includes a chip mounting region in which the semiconductor chips are arranged in a form of a matrix, and a resin injection region extending from an end of the chip mounting region,

the chip mounting region is defined by three sides and one side that corresponds to the end of the chip mounting region, and the form of the matrix is defined by three sides and one side that overlaps said one side of the chip mounting region in a plan view,

an entirety of the three sides of the chip mounting region is positioned inward of an entirety of the three sides of the form of the matrix, and the resin injection region protrudes outward of said one side of the form of the matrix in the plan view,

the plurality of semiconductor chips include a first semiconductor chip and a second semiconductor chip,

a perimeter of each of the first semiconductor chip and the second semiconductor chip is defined by first and second opposite sides and third and fourth opposite sides each connecting the first and second opposite sides,

a perimeter of the wiring substrate is defined by first and second opposite sides and third and fourth opposite sides each connecting the first and second opposite sides of the wiring substrate,

an entirety of the first side of the first semiconductor chip is positioned outward of the first side of the wiring substrate,

an entirety of the first side of the second semiconductor chip is positioned outward of the first side of the wiring substrate and an entirety of the third side of the second semiconductor chip is positioned outward of the third side of the wiring substrate, and

the third side of the first semiconductor chip faces the fourth side of the second semiconductor chip.

2. The semiconductor device as claimed in claim 1 , wherein an amount of protrusion of the resin injection region from said one side of the form of the matrix is more than or equal to 1 mm.

3. A semiconductor device array comprising:

a support; and

a plurality of semiconductor devices each being the semiconductor device as set forth in claim 1 , the semiconductor devices being arranged on the support such that respective sides of the semiconductor devices from which sides the respective wiring substrates do not protrude are adjacent to each other.

4. A semiconductor device comprising:

a wiring substrate; and

a plurality of semiconductor chips of a same size mounted on the wiring substrate by flip chip bonding with a resin being interposed between the wiring substrate and the semiconductor chips,

wherein the wiring substrate includes a chip mounting region in which the semiconductor chips are arranged in a form of a matrix of m rows and n columns, where m and n are natural numbers, at least one of m and n is greater than one, and each of the m rows has a same number of semiconductor chips and each of n columns has a same number of semiconductor chips, and a resin injection region extending from an end of the chip mounting region,

the chip mounting region is defined by three sides and one side that corresponds to the end of the chip mounting region, and the form of the matrix is defined by three sides and one side that overlaps said one side of the chip mounting region in a plan view, and

an entirety of the three sides of the chip mounting region is positioned inward of an entirety of the three sides of the form of the matrix, and the resin injection region protrudes outward of said one side of the form of the matrix in the plan view.

5. The semiconductor device as claimed in claim 4 , wherein the three sides and said one side of the form of the matrix form a line connecting sides of the semiconductor chips, the sides not facing adjacent semiconductor chips among the semiconductor chips.

6. The semiconductor device as claimed in claim 4 , wherein an amount of protrusion of the resin injection region from said one side of the form of the matrix is more than or equal to 1 mm.

7. A semiconductor device array comprising:

a support; and

a plurality of semiconductor devices each being the semiconductor device as set forth in claim 4 , the semiconductor devices being arranged on the support such that respective sides of the semiconductor devices from which sides the respective wiring substrates do not protrude are adjacent to each other.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 22, 2020
From: YAMANO, TAKAHARU; IHARA, YOSHIHIRO
To: SHINKO ELECTRIC INDUSTRIES CO., LTD.
Reel/Frame 052462/0266 →
Priority Claims (1)
JP JP2019-093518 · May 17, 2019 · national
Continuity (1)
Related Publication 20200365556A1 · Nov 19, 2020
Cited By (1)
US 12,431,439