Semiconductor device, semiconductor wafer, memory device, and electronic device
An object is to provide a semiconductor device with large memory capacity. The semiconductor device includes first to seventh insulators, a first conductor, and a first semiconductor. The first conductor is positioned on a first top surface of the first insulator and a first bottom surface of the second insulator. The third insulator is positioned in a region including a side surface and a second top surface of the first insulator, a side surface of the first conductor, and a second bottom surface and a side surface of the second insulator. The fourth insulator, the fifth insulator, and the first semiconductor are sequentially stacked on the third insulator. The sixth insulator is in contact with the fifth insulator in a region overlapping the first conductor. The seventh insulator is positioned in a region including the first semiconductor and the sixth insulator.
1. A semiconductor device comprising:
a first insulator, a second insulator, a third insulator, a fourth insulator, a fifth insulator, a sixth insulator, a seventh insulator, a first conductor, a second conductor, a first semiconductor, a second semiconductor, and a third semiconductor,
wherein:
the first conductor is positioned on a first top surface of the first insulator and on a first bottom surface of the second insulator,
the second conductor is positioned on a top surface of the second insulator and on a bottom surface of the third insulator,
the third semiconductor is positioned on a side surface of the first conductor,
the fourth insulator is positioned in a region comprising a side surface of the first insulator, a second top surface of the first insulator, the third semiconductor, a second bottom surface of the second insulator, a side surface of the second insulator, a side surface of the second conductor and a side surface of the third insulator,
the first semiconductor is in contact with the fourth insulator,
the fifth insulator is in contact with the first semiconductor in a region overlapping the first conductor with the fourth insulator and the third semiconductor positioned between the first semiconductor and the first conductor,
the sixth insulator is positioned in a region comprising:
the first semiconductor in a region overlapping the first insulator, in a region overlapping the second insulator, in a region overlapping the second conductor, in a region overlapping the third insulator; and
the fifth insulator,
the second semiconductor is in contact with the sixth insulator, and the seventh insulator is in contact with the second semiconductor.
2. The semiconductor device according to claim 1 , further comprising a third conductor in contact with the seventh insulator.
3. The semiconductor device according to claim 1 ,
wherein the first semiconductor comprises a low-resistance region at and around an interface with the sixth insulator, and
wherein the first semiconductor comprises a channel formation region in a region overlapping the first conductor.
4. The semiconductor device according to claim 3 ,
wherein the first semiconductor comprises a metal oxide,
wherein the low-resistance region comprises a conductive compound, and
wherein the conductive compound comprises a component identical to a component included in the metal oxide and a component identical to a component included in the sixth insulator.
5. The semiconductor device according to claim 3 ,
wherein the first semiconductor comprises a metal oxide,
wherein the low-resistance region comprises a conductive compound, and
wherein the conductive compound comprises a component identical to a component included in the metal oxide, and a metal element.
6. A semiconductor wafer comprising:
a plurality of the semiconductor devices according to claim 1 ; and
a region to be subjected to dicing.
7. A memory device comprising:
the semiconductor device according to claim 1 ; and
a peripheral circuit.
8. An electronic device comprising:
the memory device according to claim 7 ; and
a housing.