Semiconductor device with a through electrode reception part wider than a through electrode, solid-state imaging device, and electronic equipment
The present technology relates to a semiconductor device, a solid-state imaging device, and electronic equipment, which are able to suppress increase of resistivity to a high level at a connection portion between an ESV and a wiring layer and to improve reliability of an electric connection using an ESV. The semiconductor device according to the present technology has a plurality of semiconductor substrates layered, and includes a through electrode penetrating a silicon layer of the semiconductor substrates, a wiring layer formed inside the semiconductor substrates, and a through electrode reception part. The through electrode reception part is connected to the wiring layer, in which the through electrode has a width smaller than the through electrode reception part, and the through electrode is electrically connected to the wiring layer via the through electrode reception part. The present technology is applicable, for example, to a CMOS image sensor.
1. A semiconductor device, comprising:
a plurality of semiconductor substrates;
a through electrode that penetrates a silicon layer of the plurality of semiconductor substrates;
a wiring layer inside the plurality of semiconductor substrates; and
a through electrode reception part connected to the wiring layer, wherein
a width of the through electrode is smaller than a width of the through electrode reception part,
the through electrode is electrically connected to the wiring layer via the through electrode reception part,
each of the through electrode reception part and the wiring layer includes copper, and
the through electrode reception part is formed concurrently with the wiring layer by a dual damascene method.
2. The semiconductor device according to claim 1 , wherein the through electrode includes tungsten.
3. The semiconductor device according to claim 1 , wherein a barrier metal is at an interface between the through electrode reception part and the through electrode.
4. The semiconductor device according to claim 3 , wherein the barrier metal is on a side wall of the through electrode.
5. The semiconductor device according to claim 4 , wherein the barrier metal includes one of titanium or titanium nitride.
6. The semiconductor device according to claim 1 , wherein the through electrode includes a TSV (Through Silicon Via).
7. The semiconductor device according to claim 6 , wherein
a diameter of the through electrode is 1 μm or less, and
an aspect ratio of the through electrode is 10 or more.
8. A solid-state imaging device, comprising:
a plurality of semiconductor substrates;
a PD (photodiode) on at least one of the plurality of the semiconductor substrates;
a through electrode that penetrates a silicon layer of the plurality of semiconductor substrates;
a wiring layer inside the plurality of semiconductor substrates; and
a through electrode reception part connected to the wiring layer, wherein
a width of the through electrode is smaller than a width of the through electrode reception part,
the through electrode is electrically connected to the wiring layer via the through electrode reception part,
each of the through electrode reception part and the wiring layer includes copper, and
the through electrode reception part is formed concurrently with the wiring layer by a dual damascene method.
9. An electronic equipment, comprising:
a plurality of semiconductor substrates;
a through electrode that penetrates a silicon layer of the plurality of semiconductor substrates;
a wiring layer inside the plurality of semiconductor substrates; and
a through electrode reception part connected to the wiring layer, wherein
a width of the through electrode is smaller than a width of the through electrode reception part,
the through electrode is electrically connected to the wiring layer via the through electrode reception part,
each of the through electrode reception part and the wiring layer includes copper, and
the through electrode reception part is formed concurrently with the wiring layer by a dual damascene method.