Testing of integrated circuits during at-speed mode of operation
Methods for testing an application specific integrated circuit (ASIC). A set of representations is created that overlays power density information and clock gate physical locations of a set of clock gates in a critical sub-chip of the ASIC for test mode power analysis. The set of representations are further grouped in the sub-chip into various groups based on overlapping of the set of representations. Then, a set of test control signals is generated corresponding to each of the set of clock gates during at-speed test mode of operation such that each clock gate with overlapping representations receive different test control signals. Further, patterns are generated using a virtual constraint function to selectively enable the set of test control signals such that the set of test control signals are not activated simultaneously.
1. A method comprising:
performing an IR drop analysis for an integrated circuit (IC), the IR drop analysis including:
performing a static IR drop analysis for the IC, the static IR drop analysis identifying a first region of the IC having a maximum average power hotspot; and
performing a dynamic IR drop analysis for the first region, the dynamic IR drop analysis identifying a second region of the IC having an instantaneously high IR drop, the second region including clock gate circuits;
determining, for each clock gate circuit, a respective representation indicating power density within a respective area of the second region including the clock gate circuit;
determining, from the representations, a first area including a first clock gate circuit and a second area including a second clock gate circuit, in which the first and second areas at least partially overlap;
determining a first test control signal for the first clock gate circuit and a second test control signal for the second clock gate circuit, the first test control signal having a timing offset from the second test control signal.
2. The method of claim 1 , wherein determining the respective representations includes:
identifying eligible clock gate circuits of the clock gate circuits;
extracting location and load information for the eligible clock gate circuits; and
computing the respective representations based on the location and load information.
3. The method of claim 1 , wherein determining the first and second areas at least partially overlap includes:
extracting overlap graphs from the representations; and
running a coloring scheme on the overlap graphs to determine a mapping of preliminary test control signals for the first and second clock gate circuits.
4. The method of claim 3 , wherein running the coloring scheme includes:
creating a clock gate connectivity matrix; and
reassigning the color scheme incrementally across the overlap graphs.
5. The method of claim 1 , further comprising:
generating patterns using a virtual constraint function to selectively enable the first and second test control signals with the timing offset.
6. The method of claim 5 , wherein generating the patterns includes:
receiving values of the first and second test control signals;
checking for a contention corresponding to the values where more than one of the values is a logic 1; and
removing a pattern associated with the contention.
7. A computer system comprising:
a processor or logic circuitry configured to:
perform an IR drop analysis for an integrated circuit (IC), the IR drop analysis including:
performing a static IR drop analysis for the IC, the static IR drop analysis identifying a first region of the IC having a maximum average power hotspot; and
performing a dynamic IR drop analysis for the first region, the dynamic IR drop analysis identifying a second region of the IC having an instantaneously high IR drop, the second region including clock gate circuits;
determine, for each clock gate circuit, a respective representation indicating power density within a respective area of the second region including the clock gate circuit;
determine, from the representations, a first area including a first clock gate circuit and a second area including a second clock gate circuit, in which the first and second areas at least partially overlap;
determine a first test control signal for the first clock gate circuit and a second test control signal for the second clock gate circuit, the first test control signal having a timing offset from the second test control signal.
8. The computer system of claim 7 , wherein the processor or logic circuitry configured to determine the respective representations includes:
identifying eligible clock gate circuits of the clock gate circuits;
extracting location and load information for the eligible clock gate circuits; and
computing the respective representations based on the location and load information.
9. The computer system of claim 7 , wherein the processor or logic circuitry configured to determine the first and second areas at least partially overlap includes:
extracting overlap graphs from the representations; and
running a coloring scheme on the overlap graphs to determine a mapping of preliminary test control signals for the first and second clock gate circuits.
10. The computer system of claim 9 , wherein running the coloring scheme includes:
creating a clock gate connectivity matrix; and
reassigning the color scheme incrementally across the overlap graphs.
11. The computer system of claim 7 , wherein the processor or logic circuitry is further configured to:
generate patterns using a virtual constraint function to selectively enable the first and second test control signals with the timing offset.
12. The computer system of claim 11 , wherein generating the patterns includes:
receiving values of the first and second test control signals;
checking for a contention corresponding to the values where more than one of the values is a logic 1; and
removing a pattern associated with the contention.
13. A test system comprising:
an integrated circuit (IC); and
a computer system including a processor or logic circuitry, the processor or logic circuitry configured to:
perform an IR drop analysis for the IC, the IR drop analysis including:
performing a static IR drop analysis for the IC, the static IR drop analysis identifying a first region of the IC having a maximum average power hotspot; and
performing a dynamic IR drop analysis for the first region, the dynamic IR drop analysis identifying a second region of the IC having an instantaneously high IR drop, the second region including clock gate circuits;
determine, for each clock gate circuit, a respective representation indicating power density within a respective area of the second region including the clock gate circuit;
determine, from the representations, a first area including a first clock gate circuit and a second area including a second clock gate circuit, in which the first and second areas at least partially overlap;
determine a first test control signal for the first clock gate circuit and a second test control signal for the second clock gate circuit, the first test control signal having a timing offset from the second test control signal.
14. The test system of claim 13 , wherein the processor or logic circuitry configured to determine the respective representations includes:
identifying eligible clock gate circuits of the clock gate circuits;
extracting location and load information for the eligible clock gate circuits; and
computing the respective representations based on the location and load information.
15. The test system of claim 13 , wherein the processor or logic circuitry configured to determine the first and second areas at least partially overlap includes:
extracting overlap graphs from the representations; and
running a coloring scheme on the overlap graphs to determine a mapping of preliminary test control signals for the first and second clock gate circuits.
16. The test system of claim 15 , wherein running the coloring scheme includes:
creating a clock gate connectivity matrix; and
reassigning the color scheme incrementally across the overlap graphs.
17. The test system of claim 13 , wherein the processor or logic circuitry is further configured to:
generate patterns using a virtual constraint function to selectively enable the first and second test control signals with the timing offset.
18. The test system of claim 17 , wherein generating the patterns includes:
receiving values of the first and second test control signals;
checking for a contention corresponding to the values where more than one of the values is a logic 1; and
removing a pattern associated with the contention.