Semiconductor isolation structures having different configurations in different device regions and method of forming the same

1. A semiconductor isolation structure, comprising:

a substrate having a first trench in a first region of the substrate and a second trench in a second region of the substrate;

a filling layer in the first trench and the second trench;

a liner layer on sidewalls and bottoms of the first trench and the second trench;

a fixed negative charge layer between the filling layer and the liner layer in the first trench and the second trench; and

a fixed positive charge layer located between the fixed negative charge layer and the liner layer in the first trench,

wherein the liner layer, the fixed positive charge layer, the fixed negative charge layer and the filling layer in the first trench form a first isolation structure; and

the liner layer, the fixed negative charge layer and the filling layer in the second trench form a second isolation structure,

wherein a top surface of the fixed negative charge layer in the first trench is higher than a top surface of the fixed positive charge layer,

wherein the top surface of the fixed negative charge layer in the first trench is higher than a top surface of the fixed negative charge layer in the second trench.

2. The semiconductor isolation structure of claim 1 , wherein the first region comprises a P-type metal oxide semiconductor region, and the second region comprises an N-type metal oxide semiconductor region.

3. The semiconductor isolation structure of claim 2 , wherein the liner layer comprises a silicon oxide layer, the fixed negative charge layer includes a fixed negative charge silicon nitride layer, and the fixed positive charge layer includes a fixed positive charge silicon oxide layer.

4. The semiconductor isolation structure of claim 1 , wherein the second trench is free of the fixed positive charge layer therein.

5. The semiconductor isolation structure of claim 2 , wherein the first region and the second region are peripheral circuit regions, and the substrate further includes a third isolation structure located in a memory cell region of the substrate, the third isolation stricture comprises the liner layer and free of the fixed positive charge layer, the fixed negative charge layer and the filling layer therein.

6. The semiconductor isolation structure of claim 1 , wherein a distance between the fixed negative charge layer in the first trench and a sidewall of the first trench is greater than a distance between the fixed negative charge layer in the second trench and a sidewall of the second trench.

7. The semiconductor isolation structure of claim 1 , wherein in the first trench, the top surface of the fixed positive charge layer is lower than a top surface of the liner layer.

8. A method for forming a semiconductor isolation structure comprising:

forming a first trench in a P-type metal oxide semiconductor region of a substrate, and forming a second trench in an N-type metal oxide semiconductor region of the substrate;

forming a liner layer to cover sidewalls and bottoms of the first trench and the second trench;

forming a fixed positive charge layer to cover the liner layer in the first trench;

forming a fixed negative charge layer to cover the fixed positive charge layer in the first trench and the liner layer in the second trench; and

forming a filling layer in the first trench and the second trench to cover the fixed negative charge layer,

wherein the fixed negative charge layer is located between the filling layer and the liner layer in the first trench and the second trench, and the fixed positive charge layer is located between the fixed negative charge layer and the liner layer in the first trench;

wherein the liner layer, the fixed positive charge layer, the fixed negative charge layer and the filling layer in the first trench form a first isolation structure; and the liner layer, the fixed negative charge layer and the filling layer in the second trench form a second isolation structure; and

wherein a top surface of the fixed negative charge layer in the first trench is higher than a top surface of the fixed positive charge layer,

wherein the top surface of the fixed negative charge layer in the first trench is higher than a top surface of the fixed negative charge layer in the second trench.

9. The method of claim 8 , wherein the forming the fixed positive charged layer comprises forming a fixed positive charged silicon oxide layer by a thermal oxidation method or a chemical vapor deposition method, and the forming the fixed negative charge layer comprises forming a fixed negative charge silicon nitride layer by chemical vapor deposition, and the forming the liner layer comprises a thermal oxidation method.

10. The method of claim 8 further comprising:

forming a third trench in the memory cell region of the substrate; and

forming the liner layer in the third trench.

11. The method of claim 8 , wherein the method for forming the fixed positive charge layer includes:

forming a fixed positive charge material layer in the P-type metal oxide semiconductor region and the N-type metal oxide semiconductor region;

forming a mask layer to cover the fixed positive charge material layer in the P-type metal oxide semiconductor region;

removing the fixed positive charge layer not covered by the mask layer;

removing the mask layer; and

removing the fixed positive charge material layer except the first trench.

12. The semiconductor isolation structure of claim 1 , wherein the top surface of the fixed positive charge layer is level with the top surface of the fixed negative charge layer in the second trench.