Nonvolatile memory device and program method of the same
A program method of a nonvolatile memory device that performs a plurality of program loops is provided. At least one of the plurality of program loops includes dividing a channel of a selected cell string into a first side channel and a second side channel during a first interval and a second interval, turning off a string selection transistor of the selected cell string by applying a string select line voltage of a first level during the first interval, and boosting a first voltage of the first side channel and a second voltage of the second side channel, and turning on the string selection transistor by applying the string select line voltage of a second level different from the first level during the second interval, and performing a hot carrier injection (HCI) program operation on a selected memory cell corresponding to the first side channel or the second side channel.
1. A program method of a 3-dimensional memory device, the program method comprising:
performing a plurality of first program loops for a first selected memory cell connected to a first selected word line based on a first program method; and
performing a plurality of second program loops for a second selected memory cell connected to a second selected word line based on a second program method,
wherein a first step pattern of a plurality of first program voltages used in each of the plurality of first program loops is changed from a predetermined program loop among the plurality of first program loops,
wherein a second step pattern of a plurality of second program voltages used in each of the plurality of second program loops is based on a constant offset,
wherein a voltage level of the first step pattern used in two or more program loops of the plurality of first program loops before the predetermined program loop increases based on the constant offset, and
wherein a level variance between a first program voltage of the plurality of first program voltages applied to the first selected word line in the predetermined program loop and a second program voltage of the plurality of first program voltages applied to the first selected word line in the immediately previous program loop of the predetermined program loop is different from a level variance between the first program voltage and a third program voltage of the plurality of first program voltages applied to the first selected word line in the next program loop of the predetermined program loop.
2. The program method of claim 1 , wherein the first step pattern is changed from a pattern in which a voltage level used in each of the plurality of first program loops before the predetermined program loop increases by an offset to a pattern in which a voltage level used in each of the others of the plurality of first program loops is maintained at a constant level.
3. The program method of claim 1 , wherein a voltage level of the first step pattern increases by a first offset and then decreases by a predetermined level, and then increases by a second offset.
4. The program method of claim 3 , wherein the first and second offsets are variable according to a temperature condition of the 3-dimensional memory device.
5. The program method of claim 3 , wherein the predetermined program loop is variable according to a temperature condition of the 3-dimensional memory device.
6. The program method of claim 1 , wherein a first diameter of a channel hole corresponding to the first selected memory cell is larger than a second diameter of a channel hole corresponding to the second selected memory cell.
7. The program method of claim 1 , wherein the first selected word line is located closer to a string select line than the second selected word line.
8. The program method of claim 1 , wherein some of the plurality of first program loops before the predetermined program loop are performed based on a F-N tunneling program operation method, and the others of the plurality of second program loops are performed based on the F-N tunneling program operation method and a hot carrier injection (HCI) program method.
9. A 3-dimensional memory device, comprising:
a memory block including a plurality of vertically stacked memory cells; and
a control logic configured to control a program operation for the memory block,
wherein the control logic is configured to:
control a first program method to be changed based on a predetermined program loop among a plurality of first program loops for a first selected memory cells connected to a first selected word line of the memory block,
control a second program method for a second selected memory cells connected to a second selected word line of the memory block,
control a voltage level of a first step pattern of program voltages used in two or more program loops of the plurality of first program loops before the predetermined program loop to increase based on a constant offset, and
control a level variance between a first program voltage of the plurality of first program voltages applied to the first selected word line in the predetermined program loop and a second program voltage of the plurality of first program voltages applied to the first selected word line in the immediately previous program loop of the predetermined program loop being different from a level variance between the first program voltage and a third program voltage of the plurality of first program voltages applied to the first selected word line in the next program loop of the predetermined program loop.
10. The 3-dimensional memory device of claim 9 , wherein the control logic is configured to:
control some of the plurality of first program loops before the predetermined program loop based on a F-N tunneling program operation method,
control the others of the plurality of first program loops based on the F-N tunneling program operation method and a hot carrier injection (HCI) program operation method, and
control all of a plurality of second program loops based on the F-N tunneling program operation method.
11. The 3-dimensional memory device of claim 9 , wherein the control logic is configured to control a voltage level of a first step pattern of the program voltages used in two or more program loops of the plurality of first program loops to change from a pattern in which the voltage level increases by an offset to a pattern in which the voltage level is maintained at a constant level.
12. The 3-dimensional memory device of claim 9 , wherein the control logic is configured to control a voltage level of a first step pattern of the program voltages used in two or more program loops of the plurality of first program loops to increase by a first offset and then decrease by a predetermined level, and then increase by a second offset.
13. The 3-dimensional memory device of claim 9 , wherein the first selected word line is located between a string select line of the memory block and a reference word line of the memory block, and
wherein the second selected word line is located between the reference word line and a ground select line of the memory block.