Operation method of memory device using pass voltages
An operation method of a memory device includes a plurality of memory cells stacked in a direction perpendicular to a substrate and a plurality of word lines respectively connected with the plurality of memory cells. The method includes applying a 0-th pass voltage to a first selected word line among the plurality of word lines and applying a first pass voltage to a first upper adjacent word line among the plurality of word lines, during a first word line setup period, and applying a first program voltage to the first selected word line and applying a second pass voltage smaller than the first pass voltage to the first upper adjacent word line, during a first program execution period after the first word line setup period. The first upper adjacent word line is a word line physically adjacent to the first selected word line.
1 . An operation method of a memory device which includes a plurality of memory cells stacked in a direction perpendicular to a substrate and a plurality of word lines respectively connected with the plurality of memory cells, the method comprising:
during a first word line setup period,
applying a 0-th pass voltage to a first selected word line among the plurality of word lines,
applying a first pass voltage to a first upper adjacent word line among the plurality of word lines, the 0-th pass voltage and the first pass voltage being different voltages, and
applying the 0-th pass voltage to remaining unselected word lines of the plurality of word lines other than the first selected word line and the first upper adjacent word line; and
during a first program execution period after the first word line setup period,
applying a first program voltage to the first selected word line, and
applying a second pass voltage smaller than the first pass voltage to the first upper adjacent word line, and
applying the 0-th pass voltage to the remaining unselected word lines of the plurality of word lines other than the first selected word line and the first upper adjacent word line,
wherein the first upper adjacent word line is a word line physically adjacent to the first selected word line, and
wherein each of the 0-th, first, and second pass voltages has a level to turn on the plurality of memory cells.
2 . The method of claim 1 , wherein the first pass voltage is greater than the 0-th pass voltage.
3 . The method of claim 1 , wherein the first upper adjacent word line is a word line connected with memory cells being completely programmed from among word lines adjacent to the first selected word line.
4 . The method of claim 1 , wherein the first upper adjacent word line is a highest word line from the substrate from among word lines adjacent to the first selected word line.
5 . The method of claim 1 , further comprising:
after the first program execution period, applying at least one of a plurality of program verification voltages to the first selected word line.
6 . The method of claim 1 , further comprising:
during a second word line setup period, applying the 0-th pass voltage to a second selected word line among the plurality of word lines and applying a third pass voltage to a second upper adjacent word line among the plurality of word lines; and
during a second program execution period after the second word line setup period, applying a second program voltage to the second selected word line and applying a fourth pass voltage to the second upper adjacent word line,
wherein a first distance from the first selected word line to the first upper adjacent word line is smaller than a second distance from the second selected word line to the second upper adjacent word line, and
wherein the third pass voltage is greater than the first pass voltage and the fourth pass voltage is greater than the second pass voltage.
7 . The method of claim 6 , wherein the third pass voltage is greater than the fourth pass voltage.
8 . The method of claim 6 , wherein the third pass voltage is identical to the fourth pass voltage.
9 . The method of claim 6 , wherein the third pass voltage is smaller than the fourth pass voltage.
10 . The method of claim 1 , further comprising:
during the first program execution period, applying a fourth pass voltage to a first lower adjacent word line among the plurality of word lines,
wherein the first lower adjacent word line is a word line physically adjacent to the first selected word line.
11 . The method of claim 10 , wherein the first lower adjacent word line is a word line connected with memory cells being not completely programmed from among word lines physically adjacent to the first selected word line.
12 . The method of claim 10 , wherein the first lower adjacent word line is a closest word line to the substrate from among word lines physically adjacent to the first selected word line.
13 . An operation method of a memory device which includes a plurality of memory cells stacked in a direction perpendicular to a substrate and a plurality of word lines respectively connected with the plurality of memory cells, the method comprising:
in a first word line setup period of a first program loop,
applying a 0-th pass voltage to a first selected word line among the plurality of word lines,
applying a first pass voltage to a first upper adjacent word line adjacent to the first selected word line from among the plurality of word lines, the 0-th pass voltage and the first pass voltage being different voltages, and
applying the 0-th pass voltage to remaining unselected word lines of the plurality of word lines other than the first selected word line and the first upper adjacent word line;
in a first program execution period of the first program loop after the first word line setup period,
applying a first program voltage to the first selected word line, and
applying a second pass voltage smaller than the first pass voltage to the first upper adjacent word line, and
applying the 0-th pass voltage to the remaining unselected word lines of the plurality of word lines other than the first selected word line and the first upper adjacent word line;
in a second word line setup period of a second program loop, applying the 0-th pass voltage to the first selected word line and applying a third pass voltage to the first upper adjacent word line; and
in a second program execution period of the second program loop after the second word line setup period, applying a second program voltage greater than the first program voltage to the first selected word line and applying a fourth pass voltage to the first upper adjacent word line, and
wherein each of the 0-th, first and second pass voltages has a level to turn on the plurality of memory cells.
14 . The method of claim 13 , wherein the third pass voltage is greater than the first pass voltage or the fourth pass voltage is greater than the second pass voltage.
15 . The method of claim 13 , wherein the first upper adjacent word line is a word line connected with memory cells being completely programmed from among word lines adjacent to the first selected word line.
16 . The method of claim 13 , wherein a first space between the first upper adjacent word line and the first selected word line is narrower than a first reference space.
17 . The method of claim 13 , further comprising:
after the first program execution period and before the second word line setup period, applying at least one of a plurality of program verification voltages to the first selected word line; and
after the second program execution period, applying at least one of the plurality of program verification voltages to the first selected word line.
18 . An operation method of a memory device which includes a plurality of memory cells stacked in a direction perpendicular to a substrate and a plurality of word lines respectively connected with the plurality of memory cells, the method comprising:
performing a first program operation on a first selected word line among of the plurality of word lines; and
performing a second program operation on a second selected word line different from the first selected word line from among of the plurality of word lines,
wherein the first program operation includes:
applying, in a first word line setup period, a 0-th pass voltage to the first selected word line and applying a first pass voltage to a first upper adjacent word line; and
applying, in a first program execution period after the first word line setup period, a first program voltage to the first selected word line and applying a second pass voltage smaller than the first pass voltage to the first upper adjacent word line,
the second program operation includes:
applying, in a second word line setup period, the 0-th pass voltage to the second selected word line and applying a third pass voltage greater than the first pass voltage to a second upper adjacent word line; and
applying, in a second program execution period after the second word line setup period, the first program voltage to the second selected word line and applying a fourth pass voltage greater than the second pass voltage to the second upper adjacent word line,
a first distance from the first selected word line to the first upper adjacent word line is smaller than a second distance from the second selected word line to the second upper adjacent word line.
19 . The method of claim 18 , wherein the first upper adjacent word line is a word line, which is connected with the plurality of memory cells being completely programmed at a point in time of the first program operation, from among word lines adjacent to the first selected word line, and
wherein the second upper adjacent word line is a word line, which is connected with the plurality of memory cells being completely programmed at a point in time of the second program operation, from among word lines adjacent to the second selected word line.