IP Library › Granted Patent US 11,355,700
Granted Patent B2
US 11,355,700 · App. 16/732,359 · Granted Jun 7, 2022

Semiconductor device and method for fabricating the same

Inventors: Hui-Lin Wang (Taipei, TW); Po-Kai Hsu (Tainan, TW); Hung-Yueh Chen (Hsinchu, TW); Yu-Ping Wang (Hsinchu, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L43/12H01L43/02H01L27/222H01L43/10
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Quick Facts
Patent No.
US 11,355,700
App. No.
16/732,359
Granted
Jun 7, 2022
Kind
B2
Abstract

A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a top electrode on the MTJ stack; performing a first patterning process to remove the MTJ stack for forming a first MTJ; forming a first inter-metal dielectric (IMD) layer around the first MTJ; and performing a second patterning process to remove the first MTJ for forming a second MTJ and a third MTJ.

Claims (15)

1. A semiconductor device, comprising:

a magnetic tunneling junction (MTJ) on a substrate;

a top electrode on the MTJ;

a first cap layer adjacent to and directly contacting one side of the MTJ and the top electrode, wherein the first cap layer is made of dielectric material;

a second cap layer adjacent to another side of the MTJ; and

a first inter-metal dielectric (IMD) layer around the MTJ, wherein a top surface of the first cap layer is higher than top surfaces of the first IMD layer and the second cap layer.

2. The semiconductor device of claim 1 , further comprising:

a metal interconnection under the MTJ; and

a second IMD layer around the metal interconnection, wherein the first cap layer is adjacent to the top electrode and the MTJ and on the second IMD layer.

3. The semiconductor device of claim 2 , further comprising:

a stop layer on the first IMD layer and the top electrode; and

a hard mask on the stop layer.

4. The semiconductor device of claim 3 , wherein a sidewall of the stop layer is aligned with a sidewall of the top electrode.

5. The semiconductor device of claim 3 , wherein a sidewall of the hard mask is aligned with a sidewall of the top electrode.

6. The semiconductor device of claim 3 , wherein the first cap layer is on the hard mask.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 2, 2020
From: WANG, HUI-LIN; HSU, PO-KAI; CHEN, HUNG-YUEH; WANG, YU-PING
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 051396/0797 →
Priority Claims (1)
TW 108144115 · Dec 3, 2019 · national
Continuity (1)
Related Publication 20210167281A1 · Jun 3, 2021