Clip, lead frame, and substrate used in semiconductor package having engraved pattern formed thereon and the semiconductor package comprising the same

1. A lead frame used in a semiconductor package comprising:

an engraved pattern having a plurality of continuous line-form grooves formed on a metal surface of the lead frame;

first metal projections projected relatively higher than the metal surface of the lead frame at outer edges of hollow parts in the engraved pattern; and

second metal projections formed in an inner wall of the engraved pattern,

wherein the engraved pattern has a depth of 2 μm to 100 μm.

2. The lead frame of claim 1 , wherein the engraved pattern has a cross-section in a V form.

3. The lead frame of claim 1 , wherein the engraved pattern has a cross-section in a U form.

4. The lead frame of claim 1 , wherein the engraved pattern comprises any one selected from a diamond-shaped lattice pattern, a vertical line pattern, a triangle pattern, a diagonal line pattern, a square lattice pattern, a quadrangle pattern, a horizontal line pattern, a circle pattern, and a honeycomb pattern.

5. The lead frame of claim 1 , wherein the engraved pattern has a width of 5 μm to 80 μm.

6. The lead frame of claim 1 , wherein the first metal projections have a height of 0.5 μm to 50 μm.

7. A clip used in a semiconductor package comprising:

an engraved pattern having a plurality of continuous line-form grooves formed on a metal surface of the clip;

first metal projections projected relatively higher than the metal surface of the clip at outer edges of hollow parts in the engraved pattern; and

second metal projections formed in an inner wall of the engraved pattern.

8. The clip of claim 7 , wherein the engraved pattern has a cross-section in a V form.

9. The clip of claim 7 , wherein the engraved pattern has a cross-section in a U form.

10. The clip of claim 7 , wherein the engraved pattern comprises any one selected from a diamond-shaped lattice pattern, a vertical line pattern, a triangle pattern, a diagonal line pattern, a square lattice pattern, a quadrangle pattern, a horizontal line pattern, a circle pattern, and a honeycomb pattern.

11. The clip of claim 7 , wherein the engraved pattern has a depth of 2 μm to 100 μm.

12. The clip of claim 7 , wherein the engraved pattern has a width of 5 μm to 80 μm.

13. The clip of claim 7 , wherein the first metal projections have a height of 0.5 μm to 50 μm.

14. A substrate used in a semiconductor package comprising:

an engraved pattern having a plurality of continuous line-form grooves formed on a metal surface of the substrate;

first metal projections projected relatively higher than the metal surface of the substrate at outer edges of hollow parts in the engraved pattern; and

second metal projections formed in an inner wall of the engraved pattern,

wherein the engraved pattern has a depth of 2 μm to 100 μm.

15. The substrate of claim 14 , wherein the engraved pattern has a cross-section in a V form.

16. The substrate of claim 14 , wherein the engraved pattern has a cross-section in a U form.

17. The substrate of claim 14 , wherein the engraved pattern comprises any one selected from a diamond-shaped lattice pattern, a vertical line pattern, a triangle pattern, a diagonal line pattern, a square lattice pattern, a quadrangle pattern, a horizontal line pattern, a circle pattern, and a honeycomb pattern.

18. The substrate of claim 14 , wherein the engraved pattern has a width of 5 μm to 80 μm.

19. The substrate of claim 14 , wherein the first metal projections have a height of 0.5 μm to 50 μm.

20. A semiconductor package comprising:

a lead frame;

a semiconductor chip adhered on a pad of the lead frame;

a clip electrically connecting the semiconductor chip to a lead of the lead frame;

a sealing material molded to surround the periphery of the lead frame, the semiconductor chip, and the clip;

an engraved pattern having a plurality of continuous line-form grooves formed on at least one or more metal surfaces of the lead frame and the clip;

first metal projections projected relatively higher than the metal surface at outer edges of hollow parts in the engraved pattern; and

second metal projections formed in an inner wall of the engraved pattern.

21. The semiconductor package of claim 20 , wherein the engraved pattern has a cross-section in a V form.

22. The semiconductor package of claim 20 , wherein the engraved pattern has a cross-section in a U form.

23. The semiconductor package of claim 20 , wherein the engraved pattern comprises any one selected from a diamond-shaped lattice pattern, a vertical line pattern, a triangle pattern, a diagonal line pattern, a square lattice pattern, a quadrangle pattern, a horizontal line pattern, a circle pattern, and a honeycomb pattern.

24. The semiconductor package of claim 20 , wherein the engraved pattern has a depth of 2 μm to 100 μm.

25. The semiconductor package of claim 20 , wherein the engraved pattern has a width of 5 μm to 80 μm.

26. The semiconductor package of claim 20 , wherein the first metal projections have a height of 0.5 μm to 50 μm.

27. A semiconductor package comprising:

a substrate;

a semiconductor chip adhered on a metal surface of the substrate;

a lead frame adhered on the other metal surface of the substrate;

a bonding wire connecting the metal surface of the substrate, on which the lead frame is adhered, to the semiconductor chip;

a sealing material molded to surround the periphery of the substrate, the lead frame, the semiconductor chip, and the bonding wire;

an engraved pattern having a plurality of continuous line-form grooves formed on the metal surface of the substrate;

first metal projections projected relatively higher than the metal surface of the substrate at outer edges of hollow parts in the engraved pattern; and

second metal projections formed in an inner wall of the engraved pattern.

28. The semiconductor package of claim 27 , wherein the engraved pattern has a cross-section in a V form.

29. The semiconductor package of claim 27 , wherein the engraved pattern has a cross-section in a U form.

30. The semiconductor package of claim 27 , wherein the engraved pattern comprises any one selected from a diamond-shaped lattice pattern, a vertical line pattern, a triangle pattern, a diagonal line pattern, a square lattice pattern, a quadrangle pattern, a horizontal line pattern, a circle pattern, and a honeycomb pattern.

31. The semiconductor package of claim 27 , wherein the engraved pattern has a depth of 2 μm to 100 μm.

32. The semiconductor package of claim 27 , wherein the engraved pattern has a width of 5 μm to 80 μm.

33. The semiconductor package of claim 27 , wherein the first metal projections have a height of 0.5 μm to 50 μm.

34. A lead frame used in a semiconductor package comprising:

an engraved pattern having a plurality of continuous line-form grooves formed on a metal surface of the lead frame;

first metal projections projected relatively higher than the metal surface of the lead frame at outer edges of hollow parts in the engraved pattern; and

second metal projections formed in an inner wall of the engraved pattern,

wherein the first metal projections have a height of 0.5 μm to 50 μm.

35. A substrate used in a semiconductor package comprising:

an engraved pattern having a plurality of continuous line-form grooves formed on a metal surface of the substrate;

first metal projections projected relatively higher than the metal surface of the substrate at outer edges of hollow parts in the engraved pattern; and

second metal projections formed in an inner wall of the engraved pattern,

wherein the first metal projections have a height of 0.5 μm to 50 μm.