Vertical memory devices
The present disclosure relates to semiconductor structures and, more particularly, to a vertical memory devices and methods of manufacture. The structure includes: a first bit cell with a first top electrode; a second bit cell with a second top electrode; and a common bottom electrode for both the first bit cell and the second bit cell.
1. A structure comprising:
a first bit cell with a first top electrode;
a second bit cell with a second top electrode;
a common bottom electrode for both the first bit cell and the second bit cell,
a switching material included in each of the first bit cell and the second bit cell, the switching material between and contacting the first top electrode and a first side of the common bottom electrode, the switching material between and contacting the second top electrode and a second side of the common bottom electrode opposite to the first side;
an etch stop layer lining sidewals or the first top electrode and the second top electrode and contacting a portion of the switching material;
a first contact partially extending over and contacting a top surface of the first top electrode, and further contacting a top surface of the etch stop layer, and
a second contact partially extending over and contacting a top surface of the second top electrode, and further contacting a top surface of the etch stop layer.
2. The structure of claim 1 , wherein the switching material is between and directly contacting the first top electrode and the first side of the common bottom electrode and the second top electrode and the second side of the common bottom electrode.
3. The structure of claim 2 , wherein the switching material is a high-k dielectric material.
4. The structure of claim 1 , wherein the common bottom electrode is a different conductive material than the first top electrode and the second top electrode.
5. The structure of claim 1 , wherein the first bit cell and the second bit cell are vertical memory cells.
6. The structure of claim 5 , wherein the vertical memory cells are resistive random access memory (ReRAM) cells.
7. The structure of claim 2 , wherein the first top electrode is on the first side of the common bottom electrode and the second top electrode is on the second side of the common bottom electrode, and the switching material is an intervening material between the common bottom electrode and the first and second top electrodes.
8. The structure of claim 1 , further comprising an additional etch stop layer under the etch stop layer and above metallization features, wherein the additional etch stop layer hermitically seals the metallization features.
9. The structure of claim 1 , further comprising metallization features under the common bottom electrode, the first top electrode and the second top electrode, the metallization features being provided in both a periphery area and a memory area.
10. The structure of claim 9 , wherein the memory area comprises the first bit cell and the second bit cell.
11. A structure comprising:
a bottom electrode in electrical contact with a lower metallization feature;
a switching material contacting a first side of the bottom electrode and a second side of the bottom electrode opposite the first side;
a first top electrode on the switching material on a first side of the bottom electrode, so that the switching material is between the first side of the bottom electrode and the first too electrode;
a second top electrode on the switching material on a second side of the bottom electrode, so that the switching material is between the second side of the bottom electrode and the second top electrode;
an etch stop layer lining sidewals or the first top electrode and the second top electrode and contacting a portion of the switching material;
a first contact partially extending over and contacting a top surface of the first top electrode, and further contacting a top surface of the etch stop layer, and
a second contact partially extending over and contacting a top surface of the second top electrode, and further contacting a top surface of the etch stop layer,
wherein the first top electrode and the second top electrode share the bottom electrode in a 2-bit cell configuration.
12. The structure of claim 11 , wherein the first top electrode and the bottom electrode are a first bit cell and the second top electrode and the bottom electrode are a second bit cell, each of which include and are in directed contact with the switching material therebetween.
13. The structure of claim 12 , wherein the switching material is a high-k dielectric material.
14. The structure of claim 11 , wherein the first top electrode and the second top electrode are of a same material.
15. The structure of claim 14 , wherein the bottom electrode is of a different material than the first top electrode and the second top electrode.
16. The structure of claim 11 , wherein the first top electrode is on the first side of the bottom electrode and the second top electrode is on the second side of the bottom electrode, and the switching material is an intervening material between and directly contacting the bottom electrode and the first and second top electrodes.
17. The structure of claim 16 , wherein:
the etch stop layer is in contact with the first top electrode and the second top electrode, on a surface opposing to the switching material; and
an additional etch stop layer is under the etch stop layer and above the lower metallization feature, which is under the bottom electrode.
18. The structure of claim 17 , wherein the etch stop layer separates plural bottom electrodes.