Semiconductor device comprising transistors with different channel lengths
View Patent ↗It is an object to provide a display device which can favorably display a image without delayed or distorted signals. The display device includes a first gate driver and a second gate driver. The first gate driver and the second gate driver each include a plurality of flip flop circuits and a plurality of transfer signal generation circuits. Both the flip flop circuit and the transfer signal generation circuit are circuits which output a signal inputted to a first input terminal with a half clock cycle delay. In addition, an output terminal of the transfer signal generation circuit is directly connected to a first input terminal of the flip flop circuit in the next stage. Therefore, delay and distortion of the signal which is inputted from the transfer signal generation circuit to the flip flop circuit can be reduced.
1. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor,
wherein:
one of a source and a drain of the first transistor is connected to a first wiring;
the other of the source and the drain of the first transistor is connected to a second wiring configured to be supplied with a first clock signal;
one of a source and a drain of the second transistor is connected to the first wiring;
the other of the source and the drain of the second transistor is connected to a third wiring;
one of a source and a drain of the third transistor is connected to a gate of the first transistor;
the other of the source and the drain of the third transistor is directly connected to a fourth wiring;
a gate of the third transistor is directly connected to the fourth wiring;
one of a source and a drain of the fourth transistor is connected to the gate of the first transistor;
a gate of the fourth transistor is connected to a fifth wiring;
one of a source and a drain of the fifth transistor is connected to the fifth wiring;
the other of the source and the drain of the fifth transistor is connected to a sixth wiring configured to be supplied with a second clock signal;
one of a source and a drain of the sixth transistor is connected to the fifth wiring;
the other of the source and the drain of the sixth transistor is connected to the third wiring;
a gate of the sixth transistor is connected to a seventh wiring;
one of a source and a drain of the seventh transistor is connected to a gate of the fifth transistor;
the other of the source and the drain of the seventh transistor is connected to the first wiring;
a gate of the seventh transistor is connected to the first wiring;
one of a source and a drain of the eighth transistor is connected to the gate of the fifth transistor;
the other of the source and the drain of the eighth transistor is connected to the third wiring;
a gate of the eighth transistor is connected to the seventh wiring; and
a ratio of a channel width to a channel length of the fourth transistor is larger than a ratio of a channel width to a channel length of the eighth transistor.
2. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor,
wherein:
one of a source and a drain of the fourth transistor is connected to a gate of the first transistor;
a gate of the fourth transistor is connected to a first wiring;
one of a source and a drain of the eighth transistor is connected to a gate of the fifth transistor;
the other of the source and the drain of the eighth transistor is connected to a second wiring;
a gate of the eighth transistor is connected to a third wiring;
one of a source and a drain of the first transistor is connected to a fourth wiring;
the other of the source and the drain of the first transistor is connected to a fifth wiring configured to be supplied with a first clock signal; and
a ratio of a channel width to a channel length of the fourth transistor is larger than a ratio of a channel width to a channel length of the eighth transistor.
3. The semiconductor device according to claim 2 , wherein one of a source and a drain of the third transistor is connected to the gate of the first transistor.
4. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, and a fourth transistor,
wherein:
one of a source and a drain of the fourth transistor is connected to a gate of the first transistor;
a gate of the fourth transistor is connected to a first wiring;
one of a source and a drain of the second transistor is connected to a gate of the third transistor;
the other of the source and the drain of the second transistor is connected to a second wiring;
a gate of the second transistor is connected to a third wiring;
one of a source and a drain of the first transistor is connected to a fourth wiring;
the other of the source and the drain of the first transistor is connected to a fifth wiring configured to be supplied with a first clock signal; and
a ratio of a channel width to a channel length of the fourth transistor is larger than a ratio of a channel width to a channel length of the second transistor.
5. The semiconductor device according to claim 3 ,
wherein the other of the source and the drain of the third transistor is directly connected to a fifth wiring; and
wherein a gate of the third transistor is directly connected to the fifth wiring.
6. The semiconductor device according to claim 4 , further comprising:
a fifth transistor,
wherein one of a source and a drain of the fifth transistor is connected to the gate of the first transistor.
7. The semiconductor device according to claim 6 ,
wherein the other of the source and the drain of the fifth transistor is directly connected to a fifth wiring; and
wherein a gate of the fifth transistor is directly connected to the fifth wiring.