Methods of forming interconnect structures of semiconductor device

1. An interconnect structure, comprising:

a first etching stop layer;

a first dielectric layer on the first etching stop layer;

a second etching stop layer on the first dielectric layer;

a second dielectric layer and an insert layer on the second etching stop layer, wherein the inset layer is disposed between the second etching stop layer and the second dielectric layer; and

a conductive feature in the second dielectric layer, the insert layer, the second etching stop layer, the first dielectric layer and the first etching stop layer, wherein the conductive feature comprises a conductive line in the second dielectric layer and the insert layer, and a via in the first etching stop layer and the first dielectric layer;

wherein a material of the insert layer is different from the second dielectric layer and the second etching stop layer.

2. The interconnect structure of claim 1 , wherein the insert layer has a Young's modulus greater than a Young's modulus of the second dielectric layer.

3. The interconnect structure of claim 1 , wherein the insert layer has a dielectric constant less than a dielectric constant of the second etching stop layer.

4. The interconnect structure of claim 1 , wherein the insert layer and the second dielectric layer contain silicon atom, and the second etching stop layer is free of silicon atom.

5. The interconnect structure of claim 1 , wherein the conductive line is further disposed in and penetrates through the second etching stop layer.

6. The interconnect structure of claim 1 , wherein the conductive feature comprises a plurality of conductive lines, the second dielectric layer and the insert layer between two adjacent conductive lines forms a stack, and the stack has an aspect ratio greater than 2.

7. The interconnect structure of claim 1 , wherein the insert layer is in contact with the second etching stop layer.

8. The interconnect structure of claim 1 , wherein the insert layer is embedded in the second dielectric layer.

9. The interconnect structure of claim 1 , wherein the second dielectric layer comprises a first portion sandwiched between the insert layer and the second etching stop layer, and a second portion overlying the insert layer.

10. An interconnect structure, comprising:

a first dielectric layer;

an etching stop layer on the first dielectric layer;

a second dielectric layer on the etching stop layer;

an insert layer between the etching stop layer and the second dielectric layer; and

a conductive feature in the second dielectric layer, the insert layer, the etching stop layer, and the first dielectric layer, wherein the conductive feature comprises a conductive line in the second dielectric layer and the insert layer, and a via in the first dielectric layer;

wherein a material of the insert layer is different from the first dielectric layer, the second dielectric layer, and the etching stop layer.

11. The interconnect structure of claim 10 , wherein the insert layer has a Young's modulus greater than a Young's modulus of the second dielectric layer.

12. The interconnect structure of claim 10 , wherein the insert layer has a dielectric constant less than a dielectric constant of the etching stop layer.

13. The interconnect structure of claim 10 , wherein the insert layer comprises silicon nitride, silicon oxynitride, silicon oxycarbide, or combinations thereof, and the etching stop layer comprises aluminum oxide.

14. The interconnect structure of claim 10 , wherein the conductive feature comprises a dual damascene, and the dual damascene comprises the conductive line and the via, and the via is further disposed in the etching stop layer.

15. A method of forming an interconnect structure, comprising:

forming a first dielectric layer;

forming an etching stop layer on the first dielectric layer;

forming an insert layer on the etching stop layer;

forming a second dielectric layer on the insert layer and the etching stop layer, wherein the insert layer is between the etching stop layer and the second dielectric layer, and a material of the insert layer is different from the first dielectric layer, the second dielectric layer, and the etching stop layer; and

forming a conductive feature in the second dielectric layer, the insert layer, the etching stop layer, and the first dielectric layer, wherein the conductive feature comprises a conductive line in the second dielectric layer and the insert layer, and a via in the first dielectric layer; wherein forming the conductive feature comprises patterning the second dielectric layer, the insert layer and the etching stop layer to form a plurality of trench openings, comprising:

performing a first etching process on the second dielectric layer and the insert layer to form a plurality of first openings exposing the etching stop layer; and

performing a second etching process to remove the etching stop layer exposed by the first openings to form the plurality of trench openings; and

forming a plurality of conductive lines in the plurality of trench openings.

16. The method of claim 15 , wherein the insert layer has a Young's modulus greater than a Young's modulus of the second dielectric layer.

17. The method of claim 15 , wherein the insert layer has a dielectric constant less than a dielectric constant of the etching stop layer.

18. The method of claim 15 , wherein the insert layer comprises silicon nitride, silicon oxynitride, silicon oxycarbide, or combinations thereof, and the etching stop layer comprises aluminum oxide.

19. The method of claim 15 , wherein the performing the first etching process comprises forming a stack comprising the second dielectric layer and the insert layer between two adjacent trench openings, and the stack has an aspect ratio greater than 2.

20. The method of claim 18 , wherein the performing the first etching process comprises performing a dry etching process using an etchant having an etching selectivity of the second dielectric layer to the insert layer ranging from 1 to 5.