Array substrate and fabrication method thereof, array substrate motherboard and display device

1. A fabrication method of an array substrate, the array substrate comprising a display region and a bonding region outside the display region, the fabrication method comprising:

forming a bonding electrode, the bonding electrode is located in the bonding region and spaced apart from an outer edge of the bonding region;

forming a semiconductor thin film on a base substrate;

patterning the semiconductor thin film to form an active layer and an electrostatic barrier line, the electrostatic barrier line comprises one end electrically connected with the bonding electrode, and the other end extending to the outer edge of the bonding region, and resistivity of the electrostatic barrier line is larger than resistivity of the bonding electrode;

performing ion implantation on a source region and a drain region of the active layer as well as the electrostatic barrier line,

wherein after the patterning the semiconductor thin film and before the performing ion implantation, the fabrication method further comprises:

forming a gate insulating layer on a side of the active layer and the electrostatic barrier line that faces away from the base substrate;

forming a gate metal layer on a side of the gate insulating layer that faces away from the base substrate;

patterning the gate metal layer to form a gate electrode,

wherein the performing ion implantation comprises: performing ion implantation by using the gate electrode as a mask.

2. The fabrication method of the array substrate according to claim 1 , wherein:

forming the bonding electrode at a same time of patterning the gate metal layer to form the gate electrode;

the fabrication method further comprises: forming a first via hole in the gate insulating layer, the bonding electrode is electrically connected with the electrostatic barrier line through the first via hole.

3. The fabrication method of the array substrate according to claim 1 , further comprising:

forming an interlayer insulating layer on a side of the gate electrode that faces away from the base substrate;

forming a source/drain metal layer on a side of the interlayer insulating layer that faces away from the base substrate;

patterning the source/drain metal layer to form a source electrode, a drain electrode and the bonding electrode; and

forming a first via hole in the interlayer insulating layer and the gate insulating layer, the bonding electrode is electrically connected with the electrostatic barrier line through the first via hole.

4. An array substrate motherboard, comprising a plurality of array structures, each of the plurality of the array structure comprising a display region and a bonding region outside the display region, each of the plurality of the array structure further comprising:

a bonding electrode, located in the bonding region and spaced apart from an outer edge of the bonding region; and

an electrostatic barrier line, the electrostatic barrier line comprises one end electrically connected with the bonding electrode, and the other end extending to the outer edge of the bonding region, and resistivity of the electrostatic barrier line is larger than resistivity of the bonding electrode,

wherein among the plurality of array structures, the electrostatic barrier line of one of the plurality of the array structures is electrically connected with the electrostatic barrier line of another one of the plurality of the array structures,

wherein the plurality of array structures are arranged in at least two lines and comprise a first line of array structures and a second line of array structures adjacent to each other;

wherein the bonding region of each array structure in the first line of array structures is provided at a side close to the second line of array structures; and the bonding region of each array structure in the second line of array structures is provided at a side close to the first line of array structures; and

wherein each bonding region in the first line of array structures and each bonding region in the second line of array structures are electrically connected to each other in a one-to-one manner through the same electrostatic barrier line.

5. The array substrate motherboard according to claim 4 , wherein the array substrate motherboard further comprises an electrostatic protection line; in a direction parallel to the array substrate motherboard, the electrostatic protection line is spaced apart from the array structure, and the electrostatic barrier line is electrically connected with the electrostatic protection line.

6. The array substrate motherboard according to claim 5 , wherein the electrostatic protection line is provided corresponding to a line of array structures, a bonding region of each array structure in the line of array structures is provided at a side close to the electrostatic protection line; and electrostatic barrier lines of each array structure in the line of array structures are electrically connected with the electrostatic protection line.

7. The array substrate motherboard according to claim 5 , wherein the electrostatic protection line is provided corresponding to two lines of array structures and provided between the two lines of array structures; a bonding region of each array structure in the two lines of array structures is at a side close to the electrostatic protection line, and electrostatic barrier lines of each array structure in the two lines of the array structures are electrically connected with the electrostatic protection line.

8. The array substrate motherboard according to claim 4 , further comprising a base substrate, an active layer, a source/drain metal layer and a gate metal layer, wherein the active layer, the source/drain metal layer and the gate metal layer are located on the base substrate, wherein the electrostatic barrier line and the active layer are provided in a same layer and made of a same material, and wherein the bonding electrode and one of the source/drain metal layer and the gate metal layer are provided in a same layer and made of a same material.

9. The array substrate motherboard according to claim 5 , further comprising a base substrate, an active layer, a source/drain metal layer and a gate metal layer, wherein the active layer, the source/drain metal layer and the gate metal layer are located on the base substrate, wherein the electrostatic barrier line and the active layer are provided in a same layer and made of a same material, and wherein the electrostatic protection line and one of the source/drain metal layer and the gate metal layer are provided in a same layer and made of a same material.

10. The array substrate motherboard according to claim 4 , wherein each of the plurality of the array structure comprises a plurality of bonding electrodes and a plurality of electrostatic barrier lines; and the plurality of bonding electrodes are electrically connected with the plurality of electrostatic barrier lines in one-to-one manner.

11. The array substrate motherboard according to claim 5 , wherein the plurality of the array structures are arranged in a line, and a line direction of the plurality of the array structures is parallel to a length direction of the electrostatic protection line.