System and apparatus with low power pin diode drivers
This disclosure relates to apparatus and methods for radio-frequency (RF) switching circuits, and more particularly for a PIN diode driver circuit for high speed, high repetition rate and/or high power applications. The PIN diode driver may include a dual voltage reverse bias provided to the PIN diode, which dual voltage reverse bias may be provided by a first, relatively lower voltage, power supply and a second, relatively higher voltage, power supply. The relatively lower voltage is to discharge an intrinsic layer of the PIN diode at a lower voltage than during reverse bias of the PIN diode at the second relatively higher bias voltage in order to reduce overall power consumption.
1. A variable impedance matching network comprising:
a plurality reactance elements arranged in parallel, wherein each of the reactance elements includes:
a first terminal and a second terminal;
a PIN diode arranged in series with a capacitor between the first terminal and the second terminal;
a forward bias supply switchably coupled to the PIN diode to forward bias the PIN diode;
at least one reverse bias supply switchably coupled to the PIN diode and configured to apply a first reverse bias level followed by a second reverse bias level; and
a transmission line, the transmission line positioned between the PIN diode and the forward bias supply and the transmission line is positioned between the PIN diode and the at least one reverse bias supply to pass power applied by forward bias supply and the at least one reverse bias supply to the PIN diode while suppressing an RF signal applied across the first and second terminal; and
a controller configured to, in each of the reactance elements:
control the forward bias supply to control a resistance of the PIN diode; and
control the at least one reverse bias supply to apply the first reverse bias level to discharge an intrinsic layer of the PIN diode followed by the second reverse bias level to reverse bias the PIN diode.
2. The variable impedance matching network of claim 1 , wherein a length of the transmission line is a quarter wavelength of the signal applied across the first and second terminal.
3. The variable impedance matching network of claim 1 , wherein the first reverse bias level is a first reverse bias voltage and the second reverse bias level is a second reverse bias voltage greater than the first reverse bias voltage.
4. The variable impedance matching network of claim 1 , wherein the forward bias supply is a forward bias current supply.
5. The variable impedance matching network of claim 1 , wherein the at least one reverse bias supply is a multi-level power supply.
6. The variable impedance matching network of claim 2 wherein the at least one reverse bias supply comprises a first voltage supply to provide the first reverse bias voltage and a second voltage supply to provide the second reverse bias voltage.
7. A power system, comprising:
a power supply; and
a match network coupled to the power supply, the match network comprising:
a plurality of switched capacitor components, each of the switched capacitor components comprising a capacitor connected in series with a PIN diode;
means for:
connecting a first reverse bias voltage to the PIN diodes; and
after connecting the first reverse bias voltage to the PIN diodes and before forward biasing the PIN diodes, connecting a second reverse bias voltage, greater than the first reverse bias voltage, to the PIN diodes; and
means for blocking the means for discharging from RF power applied by the power supply.
8. The power system of claim 7 , wherein the means for blocking comprises a transmission line positioned between each PIN diode and the means for discharging to pass power applied by the means for discharging to the PIN diode while suppressing the power applied by the power supply.
9. The power system of claim 8 , wherein a length of the transmission line is a quarter of a wavelength of the power applied by the power supply.
10. The power system of claim 7 , wherein the first reverse bias voltage is about 15 volts and the second reverse bias voltage is about 1500 volts.
11. The power system of claim 7 , wherein the first reverse bias voltage is about −15 volts and the second reverse bias voltage is about −1500 volts.
12. The power system of claim 7 further comprising means for adjusting at least one of the first reverse bias voltage and the second reverse bias voltage based on a switching frequency of the PIN diode.
13. The power system of claim 7 , wherein the second reverse bias voltage is with a range of 3 to 2000 times the value of the first reverse bias voltage.