Clock driver and memory device comprising the same
A clock driver comprises: a clock detector for receiving a plurality pairs of input clock signals of a predetermined clocking protocol, and for generating a protocol identifier indicative of the predetermined clocking protocol; a phase locking loop (PLL) module coupled to receive at least one pair of the plurality pairs of input clock signals, and for generating at least one pair of reference clock signals according to the received at least one pair of input clock signal; and a plurality of multiplexers coupled to the clock detector and to the PLL module. Each multiplexer is configured for receiving one pair of the plurality pairs of input clock signals and one pair of the at least one pair of reference clock signals, and selectively outputting, according to the protocol identifier, the pair of input clock signals and the pair of reference clock signals to drive a group of memory chips.
1. A clock driver, comprising:
a clock detector for receiving a plurality pairs of input clock signals of a predetermined clocking protocol, and for generating a protocol identifier indicative of the predetermined clocking protocol by determining toggling of the plurality pairs of input clock signals;
a phase locking loop (PLL) module coupled to receive at least one pair of the plurality pairs of input clock signals, and for generating at least one pair of reference clock signals according to the received at least one pair of input clock signal; and
a plurality of multiplexers coupled to the clock detector and to the PLL module, wherein each multiplexer is configured for receiving one pair of the plurality pairs of input clock signals and one pair of the at least one pair of reference clock signals, and selectively outputting, according to the protocol identifier, the pair of input clock signals and the pair of reference clock signals to drive a group of memory chips.
2. The clock driver of claim 1 , wherein the PLL module comprises a PLL unit, and all of the plurality of multiplexers are coupled to the PLL unit to receive the pair of reference clock signals generated by the PLL unit.
3. The clock driver of claim 1 , wherein the PLL module is further coupled to the clock detector to receive the protocol identifier and configured to be enabled or disabled according to the received protocol identifier.
4. The clock driver of claim 1 , wherein the clock driver further comprises:
one or more clock trees each being coupled between one of the plurality of multiplexers and a group of memory chips and being configured for introducing an offset into the pair of reference clock signals.
5. The clock driver of claim 1 , wherein each of the plurality of multiplexers comprises:
a first input coupled to receive one pair of the plurality pairs of input clock signals;
a second input coupled to the PLL module;
a control node coupled to the clock detector to receive the protocol identifier; and
an output coupled to a group of memory chips.
6. The clock driver of claim 1 , wherein the clock detector is configured for generating the protocol identifier by determining whether only one pair of the plurality pairs of input clock signals is toggling or not.
7. The clock driver of claim 6 , wherein each multiplexer is configured for outputting the pair of input clock signals when it is determined that not only one pair of the plurality pairs of input clock signals is toggling, and for outputting the pair of reference clock signals when it is determined that only one pair of the plurality pairs of input clock signals is toggling.
8. The clock driver of claim 1 , wherein the clock driver is configured to be integrated in a memory device, and the clock detector is further configured for generating the protocol identifier after a power-on signal indicative of initialization of the memory device is received.
9. The clock driver of claim 1 , wherein the predetermined clocking protocol is a memory clocking protocol without an on-board clock driver or a memory clocking protocol with an on-board clock driver.
10. The clock driver of claim 1 , wherein the PLL module comprises two or more PLL units.
11. A memory device, comprising:
a plurality groups of memory chips; and
a clock driver, wherein the clock driver comprises:
a clock detector for receiving a plurality pairs of input clock signals of a predetermined clocking protocol, and for generating a protocol identifier indicative of the predetermined clocking protocol by determining toggling of the plurality pairs of input clock signals;
a phase locking loop (PLL) module coupled to receive at least one pair of the plurality pairs of input clock signals, and for generating at least one pair of reference clock signals according to the received at least one pair of input clock signals; and
a plurality of multiplexers coupled to the clock detector and to the PLL module, wherein each multiplexer is configured for receiving one pair of the plurality pairs of input clock signals and one pair of the at least one pair of reference clock signals, and selectively outputting, according to the protocol identifier, the pair of input clock signals and the pair of reference clock signals to drive one group of the plurality groups of memory chips.
12. The memory device of claim 11 , wherein the memory device is an unbuffered dual inline memory module (UDIMM) or a small outline dual inline memory module (SODIMM).
13. The memory device of claim 11 , wherein the clock detector is configured for generating the protocol identifier by determining whether only one pair of the plurality pairs of input clock signals is toggling or not.
14. The memory device of claim 13 , wherein each multiplexer is configured for outputting the pair of input clock signals when it is determined that not only one pair of the plurality pairs of input clock signals is toggling, and for outputting the pair of reference clock signals when it is determined that only one pair of the plurality pairs of input clock signals is toggling.
15. The memory device of claim 11 , wherein the clock driver is configured to be integrated in a memory device, and the clock detector is further configured for generating the protocol identifier after a power-on signal indicative of initialization of the memory device is received.
16. A method for clocking a memory device, wherein the method comprises:
receiving a plurality pairs of input clock signals of a predetermined clocking protocol;
generating a protocol identifier indicative of the predetermined clocking protocol by determining toggling of the plurality pairs of input clock signals; and
selectively outputting, according to the protocol identifier, the plurality pairs of input clock signals or a plurality of reference clock signals generated according to at least one pair of input clock signals.
17. The method of claim 16 , wherein the method further comprises:
generating, via a phase locking loop module the plurality of reference clock signals according to the at least one pair of input clock signals.
18. The method of claim 16 , wherein generating a protocol identifier indicative of the predetermined clocking protocol by determining toggling of the plurality pairs of input clock signals comprises:
determining whether only one pair of the plurality pairs of input clock signals is toggling or not.
19. The method of claim 18 , wherein selectively outputting, according to the protocol identifier, the plurality pairs of input clock signals or a plurality of reference clock signals generated according to at least one pair of input clock signals comprises:
outputting the plurality pairs of input clock signals when it is determined that not only one pair of the plurality pairs of input clock signals is toggling, and
outputting the plurality pairs of reference clock signals when it is determined that only one pair of the plurality pairs of input clock signals is toggling.