Controlling memory module clock buffer power in a system with dual memory clocks per memory module
A clock buffer device for a memory module includes a first clock input coupled to an input of a first phase-locked loop (PLL), and a second clock input coupled to an input of a second PLL. An output of the first PLL is selectably coupled to clock output buffers, and an output of the second PLL is selectably coupled to a subset of the clock output buffers. The clock buffer device receives a first indication that a first information handling system is configured to provide a first clock signal on the first clock input but to not provide a second clock signal on the second clock input, and, in response to the indication, couples the output of the first PLL to the clock output buffers and to disables the second PLL.
1. An information handling system, comprising:
a host processing system including a first memory clock and a second memory clock; and
a memory module including:
a first rank of memory devices of a first sub-channel of memory devices;
a first rank of memory devices of a second sub-channel of memory devices; and
a clock buffer device including:
a first clock input coupled to the first memory clock;
a first phase-locked loop (PLL) selectably coupled to the first clock input;
a second clock input coupled to the second memory clock; and
a second PLL selectably coupled to the second clock input;
wherein the clock buffer device is configured:
in a first mode, to couple the first clock input via the first PLL to the first rank of memory devices of the first sub-channel and via the first PLL to the first rank of memory devices of the second sub-channel;
in a second mode, to couple the first clock input directly to the first rank of memory devices of the first sub-channel and directly to the first rank of memory devices of the second sub-channel;
in a third mode, to couple the first clock input via the first PLL to the first rank of memory devices of the first sub-channel and to couple the second clock input signal via the second PLL to the first rank of memory devices of the second sub-channel; and
in a fourth mode, to couple the first clock input directly to the first rank of memory devices of the first sub-channel and to couple the second clock input directly to the first rank of memory devices of the second sub-channel.
2. The information handling system of claim 1 , wherein the clock buffer device further includes:
a first output clock buffer for the first rank of memory devices of the first sub-channel;
a second output clock buffer for the first rank of memory devices of the second sub-channel;
a third output clock buffer for a second rank of memory devices of the first sub-channel of memory devices; and
a fourth output clock buffer for a second rank of memory devices of the second sub-channel.
3. The information handling system of claim 2 , wherein the clock buffer device is further configured:
to determine whether or not the memory module includes the second rank of memory devices of the first sub-channel and the second rank of memory devices of the second sub-channel;
when the memory module includes the second rank of memory devices of the first sub-channel and the second rank of memory devices of the second sub-channel, to enable the first clock output buffer, the second clock output buffer, the third clock output buffer, and the fourth clock output buffer; and
when the memory module does not include the second rank of memory devices of the first sub-channel and the second rank of memory devices of the second sub-channel, to enable the first clock output buffer and the second clock output buffer, and to disable the third clock output buffer and the fourth clock output buffer.
4. The information handling system of claim 1 , wherein the memory module further includes:
a second rank of memory devices of the first sub-channel; and
a second rank of memory devices of the second sub-channel.
5. The information handling system of claim 4 , wherein the clock buffer device is further configured:
to determine that the memory module includes the second rank of memory devices of the first sub-channel and the second rank of memory devices of the second sub-channel;
when the clock buffer device is in the first mode, to couple the first clock input via the first PLL to the second rank of memory devices of the first sub-channel and via the first PLL to the second rank of memory devices of the second sub-channel in response to determining that the memory module includes the second rank of memory devices of the first sub-channel and the second rank of memory devices of the second sub-channel;
when the clock buffer device is in the second mode, to couple the first clock input directly to the second rank of memory devices of the first sub-channel and directly to the second rank of memory devices of the second sub-channel in response to determining that the memory module includes the second rank of memory devices of the first sub-channel and the second rank of memory devices of the second sub-channel;
when the clock buffer device is in the third mode, to couple the first clock input via the first PLL to the second rank of memory devices of the first sub-channel and to couple the second clock input signal via the second PLL to the second rank of memory devices of the second sub-channel in response to determining that the memory module includes the second rank of memory devices of the first sub-channel and the second rank of memory devices of the second sub-channel; and
when the clock buffer device is in the fourth mode, to couple the first clock input directly to the second rank of memory devices of the first sub-channel and to couple the second clock input directly to the second rank of memory devices of the second sub-channel in response to determining that the memory module includes the second rank of memory devices of the first sub-channel and the second rank of memory devices of the second sub-channel.
6. The information handling system of claim 1 , wherein the clock buffer device enters one of the first mode, the second mode, the third mode, and the fourth mode based upon an indication from the host processing system.
7. The information handling system of claim 6 , wherein the clock buffer device further includes a clock state machine configured to receive the indication.
8. The information handling system of claim 7 , wherein the host processing system is coupled to the clock state machine via a two-wire interface to provide the indication to the clock buffer device.
9. The information handling system of claim 8 , wherein the two-wire interface is an Inter-Integrated Circuit (I2C) interface.
10. A method, comprising:
providing, on a host processing system of an information handling system, a first memory clock and a second memory clock;
providing, on a memory module, a first rank of memory devices of a first sub-channel of memory devices of the memory module;
providing, on the memory module, a first rank of memory devices of a second sub-channel of memory devices of the memory module;
providing, on a clock buffer device, a first clock input coupled to the first memory clock;
providing, on the clock buffer device, a first phase-locked loop (PLL) selectably coupled to the first clock input;
providing, on the clock buffer device, a second clock input coupled to the second memory clock;
providing, on the clock buffer device, a second PLL selectably coupled to the second clock input;
in a first mode, coupling the first clock input via the first PLL to the first rank of memory devices of the first sub-channel and via the first PLL to the first rank of memory devices of the second sub-channel;
in a second mode, coupling the first clock input directly to the first rank of memory devices of the first sub-channel and directly to the first rank of memory devices of the second sub-channel;
in a third mode, coupling the first clock input via the first PLL to the first rank of memory devices of the first sub-channel and coupling the second clock input signal via the second PLL to the first rank of memory devices of the second sub-channel; and
in a fourth mode, coupling the first clock input directly to the first rank of memory devices of the first sub-channel and coupling the second clock input directly to the first rank of memory devices of the second sub-channel.
11. The method of claim 10 , further comprising:
providing, on the clock buffer device, a first output clock buffer for the first rank of memory devices of the first sub-channel;
providing, on the clock buffer device, a second output clock buffer for the first rank of memory devices of the second sub-channel;
providing, on the clock buffer device, a third output clock buffer for a second rank of memory devices of the first sub-channel of memory devices; and
providing, on the clock buffer device, a fourth output clock buffer for a second rank of memory devices of the second sub-channel.
12. The method of claim 11 , further comprising:
determining whether or not the memory module includes the second rank of memory devices of the first sub-channel and the second rank of memory devices of the second sub-channel;
when the memory module includes the second rank of memory devices of the first sub-channel and the second rank of memory devices of the second sub-channel, enabling the first clock output buffer, the second clock output buffer, the third clock output buffer, and the fourth clock output buffer; and
when the memory module does not include the second rank of memory devices of the first sub-channel and the second rank of memory devices of the second sub-channel, enabling the first clock output buffer and the second clock output buffer, and disabling the third clock output buffer and the fourth clock output buffer.
13. The method of claim 10 , further comprising:
providing, on the memory module, a second rank of memory devices of the first sub-channel; and
providing, on the memory module, a second rank of memory devices of the second sub-channel.
14. The method of claim 13 , further comprising:
determining that the memory module includes the second rank of memory devices of the first sub-channel and the second rank of memory devices of the second sub-channel;
when the clock buffer device is in the first mode, coupling the first clock input via the first PLL to the second rank of memory devices of the first sub-channel and via the first PLL to the second rank of memory devices of the second sub-channel in response to determining that the memory module includes the second rank of memory devices of the first sub-channel and the second rank of memory devices of the second sub-channel; and
when the clock buffer device is in the second mode, coupling the first clock input directly to the second rank of memory devices of the first sub-channel and directly to the second rank of memory devices of the second sub-channel in response to determining that the memory module includes the second rank of memory devices of the first sub-channel and the second rank of memory devices of the second sub-channel;
when the clock buffer device is in the third mode, coupling the first clock input via the first PLL to the second rank of memory devices of the first sub-channel and coupling the second clock input signal via the second PLL to the second rank of memory devices of the second sub-channel in response to determining that the memory module includes the second rank of memory devices of the first sub-channel and the second rank of memory devices of the second sub-channel; and
when the clock buffer device is in the fourth mode, coupling the first clock input directly to the second rank of memory devices of the first sub-channel and coupling the second clock input directly to the second rank of memory devices of the second sub-channel in response to determining that the memory module includes the second rank of memory devices of the first sub-channel and the second rank of memory devices of the second sub-channel.
15. The method of claim 10 , further comprising:
receiving, by the clock buffer device, an indication from the host processing system; and
entering one of the first mode, the second mode, the third mode, and the fourth mode based upon the indication.
16. The method of claim 15 , further comprising providing, on the clock buffer device, a clock state machine configured to receive the indication.
17. The method of claim 16 , further comprising coupling the host processing system to the clock state machine via a two-wire interface to provide the indication to the clock buffer device.
18. The method of claim 17 , wherein the two-wire interface is an inter-integrated circuit interface.
19. An information handling system, comprising:
a host processing system including a first memory clock and a second memory clock; and
a memory module including:
a first rank of memory devices of a first sub-channel of memory devices;
a first rank of memory devices of a second sub-channel of memory devices; and
a clock buffer device including:
a first clock input coupled to the first memory clock;
a first phase-locked loop (PLL) selectably coupled to the first clock input;
a second clock input coupled to the second memory clock; and
a second PLL selectably coupled to the second clock input;
wherein the clock buffer device is configured:
in a first mode, to couple the first clock input directly to the first rank of memory devices of the first sub-channel and directly to the first rank of memory devices of the second sub-channel; and
in a second mode, to couple the first clock input directly to the first rank of memory devices of the first sub-channel and directly to the first rank of memory devices of the second sub-channel;
in a third mode, to couple the first clock input via the first PLL to the first rank of memory devices of the first sub-channel and to couple the second clock input signal via the second PLL to the first rank of memory devices of the second sub-channel; and
in a fourth mode, to couple the first clock input directly to the first rank of memory devices of the first sub-channel and to couple the second clock input directly to the first rank of memory devices of the second sub-channel; and
wherein a basic input/output system of the host processing system provides an indication to configure the clock buffer device in one of the first mode and the second mode.
20. The information handling system of claim 19 , wherein the clock buffer device further includes:
a first output clock buffer for the first rank of memory devices of the first sub-channel;
a second output clock buffer for the first rank of memory devices of the second sub-channel;
a third output clock buffer for a second rank of memory devices of the first sub-channel of memory devices; and
a fourth output clock buffer for a second rank of memory devices of the second sub-channel.