System power reduction for DDR5 information handling systems
An information handling system includes a memory module having clock inputs. Clock generation logic includes clock outputs, each clock output coupled to an associated one of the clock inputs. The information handling system determines whether the memory module is in a first configuration or a second configuration, enables a first number of the clock outputs when the memory module is in the first configuration, and enables a second number of the clock outputs when the memory module is in the second configuration, the first number being different from the second number.
1 . An information handling system, comprising:
a memory module including a plurality of clock inputs; and
a system-on-a-chip (SoC) having clock generation logic including a plurality of clock outputs, each clock output coupled to provide a clock signal to an associated one of the clock inputs;
wherein the clock generation logic is configured to determine whether the memory module is a dual-rank memory module or a single-rank memory module, enable a first number of the clock outputs when the memory module is the dual-rank memory module, and enable a second number of the clock outputs when the memory module is the single-rank memory module, the first number being different from the second number.
2 . The information handling system of claim 1 , wherein the first number of clock outputs is equal to four (4) clock outputs, and the second number of clock outputs is equal to two (2) clock outputs.
3 . The information handling system of claim 1 , wherein the clock generation logic is further configured to determine whether the memory module includes a clock buffer chip.
4 . The information handling system of claim 3 , wherein, when the memory module includes the clock buffer chip, the clock generation logic is further configured to determine whether the memory module operates at greater than or equal to 6000 mega-transfers per second.
5 . The information handling system of claim 4 , wherein, when the memory module operates at greater than or equal to 6000 mega-transfers per second, the clock generation logic is further configured to enable only one (1) clock output.
6 . The information handling system of claim 4 , wherein, when the memory module operates at less than 6000 mega-transfers per second, the clock generation logic is further configured to enable the first number of the clock outputs when the memory module is the dual-rank memory module, and to enable the second number of the clock outputs when the memory module is the single-rank memory module.
7 . The information handling system of claim 1 , wherein the clock generation logic includes a single clock tree.
8 . The information handling system of claim 1 , wherein the clock generation logic includes two (2) clock trees.
9 . A method, comprising:
providing, on an information handing system, a memory module including a plurality of clock inputs;
providing, on the information handling system, a system-on-a-chip having clock generation logic including a plurality of clock outputs, each clock output coupled to provide a clock signal to an associated one of the clock inputs;
determining whether the memory module is in dual-rank memory module or a single-rank memory module;
enabling, by the clock generation logic, a first number of the clock outputs when the memory module is the dual-rank memory module; and
enabling, by the clock generation logic, a second number of the clock outputs when the memory module is the single-rank memory module, the first number being different from the second number.
10 . The method of claim 9 , wherein the first number of clock outputs is equal to four (4) clock outputs, and the second number of clock outputs is equal to two (2) clock outputs.
11 . The method of claim 9 , further comprising:
determining whether the memory module includes a clock buffer chip.
12 . The method of claim 11 , wherein, when the memory module includes the clock buffer chip, the clock generation logic is further configured to determine whether the memory module operates at greater than or equal to 6000 mega-transfers per second.
13 . The method of claim 12 , wherein, when the memory module operates at greater than or equal to 6000 mega-transfers per second, the clock generation logic is further configured to enable only one (1) clock output.
14 . The information handling system of claim 12 , wherein, when the memory module operates at less than 6000 mega-transfers per second, method further comprises:
enabling, by the clock generation logic, the first number of the clock outputs when the memory module is the dual-rank memory module; and
enabling, by the clock generation logic, the second number of the clock outputs when the memory module is the single-rank memory module.
15 . The method of claim 9 , wherein the memory module is a fifth generation double data rate (DDR5) memory module.
16 . An information handling system, comprising:
a fifth generation double data rate memory module including four (4) clock inputs; and
a system-on-a-chip having clock generation logic including four (4) clock outputs, each clock output coupled to provide a clock signal to an associated one of the clock inputs;
wherein the Clock generation logic is configured to determine whether the memory module is a dual-rank memory module or a single-rank memory module, enable four (4) clock outputs when the memory module is the dual-rank memory module and operates at less than 6000 mega-transfers per second, enable two (2) clock outputs when the memory module is the single-rank memory module and operates at less than 6000 mega-transfers per second, and enable only one (1) clock output when the memory module operates at greater than or equal to 6000 mega-transfers per second.