Physical unclonable function (PUF) chip
A physical unclonable function (PUF) chip is provided. The physical unclonable function (PUF) chip includes a chip with a top metal connection layer, an array of spaced electrode plates on the top metal connection layer of the chip, a deposition layer, on the top metal connection layer between each two adjacent electrode plates. An opening is formed between the each two adjacent electrode plates in a row, and each two adjacent electrode plates are tangential to the opening formed between the two adjacent electrode plates. The physical unclonable function (PUF) chip further includes a conductive coating layer on the chip and the conductive coating layer includes conductive particles with randomly distributed size, and a package substrate, packaged with the chip including the conductive coating layer.
1. A physical unclonable function (PUF) chip, comprising:
a chip with a top metal connection layer;
an array of spaced electrode plates on the top metal connection layer of the chip;
a deposition layer, on the top metal connection layer between each two adjacent electrode plates, wherein an opening is formed between the each two adjacent electrode plates in a row and has a diameter in a direction perpendicular to the each two adjacent electrode plates equaling a distance between the each two adjacent electrode plates, and each two adjacent electrode plates are tangential to the opening formed between the two adjacent electrode plates;
a conductive coating layer on the chip, the conductive coating layer including conductive particles with randomly distributed size; and
a package substrate, packaged with the chip including the conductive coating layer.
2. The chip according to claim 1 , wherein:
the array of spaced electrode plates are comb-shaped.
3. The chip according to claim 1 , wherein:
the conductive coating layer is coated in a region of the openings.
4. The chip according to claim 1 , wherein:
the deposition layer is formed between adjacent electrode plates in any row by an in-mold decoration (IMD) process.
5. The chip according to claim 1 , further comprising:
a detector, for detecting a connection state of a capacitor, formed by the adjacent electrode plates in a row having the deposition layer there-between; and
a storage unit, for storing a detection result of the PUF chip.
6. The chip according to claim 5 , wherein:
the storage unit is a nonvolatile memory.
7. The chip according to claim 1 , wherein:
the electrode plates in the array of spaced electrode plates have a same size.
8. The chip according to claim 1 , wherein:
the adjacent electrode plates in any row of the array of spaced electrode plates are arranged at equal intervals.
9. The chip according to claim 1 , wherein:
a capacitor formed by bridged adjacent two electrode plates is in a bridged capacitor state, and
a capacitor formed by non-bridged adjacent two electrode plates is in a normal capacitor state.
10. The chip according to claim 1 , wherein:
the conductive coating layer is directly formed in each of the openings in the deposition layer.
11. The chip according to claim 9 , wherein:
the bridged adjacent two electrode plates are electrically connected by conductive particles distributed between the bridged adjacent two electrode plates.
12. The chip according to claim 1 , wherein:
randomly distributed bridges are formed between adjacent two electrode plates due to the randomly distributed size of the conductive particles.
13. The chip according to claim 1 , wherein:
conductive particles having a diameter smaller than the diameter of the opening are in the opening.