Redistribution lines with protection layers and method forming same
A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.
1. A method comprising:
forming a metal seed layer over a first conductive feature of a wafer;
forming a patterned photo resist on the metal seed layer;
forming a second conductive feature in an opening in the patterned photo resist;
heating the wafer to generate a gap between the second conductive feature and the patterned photo resist;
plating a protection layer on the second conductive feature;
removing the patterned photo resist; and
etching the metal seed layer.
2. The method of claim 1 , wherein the heating is performed at a temperature in a range between about 40° C. and about 80° C.
3. The method of claim 1 , wherein the heating is performed for a period of time in a range between about 3 minutes and about 10 minutes.
4. The method of claim 1 , wherein the plating the protection layer comprises plating a metal layer comprising a metal selected from the group consisting of Ni, Sn, Ag, Cr, Ti, Pt, and combinations thereof.
5. The method of claim 1 further comprising:
depositing a passivation layer on the protection layer;
forming a planarization layer on the passivation layer;
etching-through the planarization layer and the passivation layer; and
forming a third conductive feature extending into the planarization layer and the passivation layer to electrically connect to the second conductive feature.
6. The method of claim 5 , wherein the third conductive feature contacts a top surface of the protection layer.
7. The method of claim 5 further comprising etching-through the protection layer, and the third conductive feature contacts a top surface of the second conductive feature.
8. A device comprising:
a first dielectric layer;
a redistribution line comprising a portion over the first dielectric layer, wherein the redistribution line comprises:
a first conductive feature; and
a protection layer comprising:
a top portion over and contacting a first top surface of the first conductive feature; and
a sidewall portion contacting a sidewall of the first conductive feature to form a vertical interface; and
a second dielectric layer extending on a sidewall and a second top surface of the redistribution line.
9. The device of claim 8 further comprising an under-bump metallurgy over and electrically connecting to the protection layer.
10. The device of claim 9 , wherein the under-bump metallurgy comprises a bottom surface contacting a top surface of the protection layer.
11. The device of claim 9 , wherein the under-bump metallurgy penetrates through the protection layer to contact the first top surface of the first conductive feature.
12. The device of claim 8 , wherein the sidewall portion of the protection layer contacts an upper part of the sidewall of the first conductive feature to form the vertical interface, and a lower part of the sidewall of the first conductive feature is in contact with the second dielectric layer.
13. The device of claim 8 , wherein the top portion of the protection layer extends laterally beyond a sidewall of the first conductive feature, and wherein the sidewall of the first conductive feature is free from the protection layer.
14. The device of claim 13 , wherein the second dielectric layer contacts an entire top surface of the top portion of the protection layer.
15. A device comprising:
a passivation layer;
a redistribution line comprising a via portion extending into the passivation layer, and a line portion over and joining to the via portion, wherein the line portion comprises:
a seed layer over the passivation layer;
a conductive material over the seed layer; and
a protection layer comprising:
a top portion over and contacting the conductive material; and
a first sidewall portion directly contacting a first sidewall of the conductive material; and
a first dielectric layer extending on the first sidewall portion and the top portion of the protection layer.
16. The device of claim 15 , wherein the protection layer further comprises a second sidewall portion contacting a second sidewall of the conductive material, wherein a first bottom end of the first sidewall portion is lower than a second bottom end of the second sidewall portion.
17. The device of claim 15 , wherein the first sidewall portion is directly over an outer portion of the seed layer.
18. The device of claim 15 , wherein the protection layer is free from portions extending to a level lower than a top surface of the seed layer.
19. The device of claim 15 , wherein the first dielectric layer comprises a first top surface and a second top surface higher than the first top surface, and the device further comprises a second dielectric layer over and contacting both of the first top surface and the second top surface of the first dielectric layer, and wherein the second dielectric layer comprises a planar top surface extending directly over both of the first top surface and the second top surface.
20. The device of claim 15 , wherein the first sidewall portion of the protection layer forms a vertical interface with the first sidewall of the conductive material.