Memory device having multiple chips and method for manufacturing the same

1. A memory device comprising:

a first chip including a first insulating layer and a first pad;

a plurality of memory units provided in a first area of the first insulating layer and arranged at first intervals along a first direction parallel to a surface of the first chip, each of the plurality of memory units including a first columnar portion extending along a second direction in the first insulating layer, the second direction being perpendicular to the surface of the first chip;

a plurality of mark portions provided in a second area of the first insulating layer and arranged at second intervals along the first direction, each of the plurality of mark portions including a second columnar portion extending along the second direction in the first insulating layer;

a second chip including a second pad connected to the first pad and overlapping the first chip along the second direction; and

a circuit provided in the second chip,

wherein

the plurality of mark portions are electrically isolated from the plurality of memory units and the circuit,

the first columnar portion includes a capacitor,

the capacitor includes a first conductive portion, a second conductive portion, and a first insulating portion between the first conductive portion and the second conductive portion,

the second columnar portion includes a third conductive portion, a fourth conductive portion, and a second insulating portion between the third conductive portion and the fourth conductive portion,

a material of the first conductive portion is identical to a material of the third conductive portion,

a material of the second conductive portion is identical to a material of the fourth conductive portion, and

a material of the first insulating portion is identical to a material of the second insulating portion.

2. The memory device of claim 1 , further comprising a plurality of first members provided in a third area between the first area and the second area in the first insulating layer, wherein:

the plurality of memory units are arranged in the first area in a first layout pattern;

the plurality of mark portions are arranged in the second area in the first layout pattern; and

the plurality of first members are arranged in the third area in a random layout pattern.

3. The memory device of claim 1 , further comprising a plurality of second members provided in the second area in a random layout pattern.

4. The memory device of claim 1 , wherein the first insulating layer is an aluminum oxide layer.

5. The memory device of claim 1 , wherein each of the plurality of memory units and each of the plurality of mark portions has a structure including a plurality of constricted portions arranged along the second direction.

6. The memory device of claim 1 , wherein each of the first and second columnar portions has a structure including a plurality of constricted portions, and the plurality of constricted portions are periodically arranged along the second direction.

7. The memory device of claim 1 , wherein

the plurality of mark portions are provided for an alignment of the first chip and the second chip.

8. A memory device comprising:

a first chip including a first insulating layer and a first pad;

a plurality of memory units provided in a first area of the first insulating layer and arranged at first intervals along a first direction parallel to a surface of the first chip;

a plurality of mark portions provided in a second area of the first insulating layer and arranged at second intervals along the first direction;

a second chip including a second pad connected to the first pad and overlapping the first chip in a second direction perpendicular to the surface of the first chip; and

a circuit provided in the second chip,

wherein each of the plurality of memory units includes a first magnetic body and a reading element connected to one end of the magnetic body.

9. The memory device of claim 8 , wherein each of the plurality of mark portions includes a second magnetic body and a first layer provided on the second magnetic body in the second direction.

10. The memory device of claim 8 , wherein:

each of the plurality of memory units includes a first columnar portion extending along the second direction in the first insulating layer; and

each of the plurality of mark portions includes a second columnar portion extending along the second direction in the first insulating layer.

11. The memory device of claim 8 , further comprising a plurality of first members provided in a third area between the first area and the second area in the first insulating layer, wherein:

the plurality of memory units are arranged in the first area in a first layout pattern;

the plurality of mark portions are arranged in the second area in the first layout pattern; and

the plurality of first members are arranged in the third area in a random layout pattern.

12. The memory device of claim 8 , further comprising a plurality of second members provided in the second area in a random layout pattern.

13. The memory device of claim 8 , wherein the first insulating layer is an aluminum oxide layer.

14. The memory device of claim 8 , wherein each of the plurality of memory units and each of the plurality of mark portions has a structure including a plurality of constricted portions arranged along the second direction.

15. The memory device of claim 14 , wherein the plurality of constricted portions are periodically arranged along the second direction.