Gate patterning process for multi-gate devices
A method includes providing first and second channel layers in a p-type region and an n-type region respectively, forming a gate dielectric layer around the first and second channel layers, and forming a sacrificial layer around the gate dielectric layer. The sacrificial layer merges in space between the first channel layers and between the second channel layers. The method further includes etching the sacrificial layer such that only portions of the sacrificial layer in the space between the first channel layers and between the second channel layers remain, forming a mask covering the p-type region and exposing the n-type region, removing the sacrificial layer from the n-type region, removing the mask, and forming an n-type work function metal layer around the gate dielectric layer in the n-type region and over the gate dielectric layer and the sacrificial layer in the p-type region.
1. A method comprising:
providing a structure having a p-type region and an n-type region, the p-type region having first channel layers, the n-type region having second channel layers;
forming a gate dielectric layer around the first channel layers and around the second channel layers;
forming a sacrificial layer around the gate dielectric layer in both the p-type region and the n-type region, wherein the sacrificial layer merges in space between the first channel layers and merges in space between the second channel layers;
etching the sacrificial layer such that only portions of the sacrificial layer in the space between the first channel layers and in the space between the second channel layers remain;
forming a first mask covering the p-type region and exposing the n-type region;
with the first mask in place, removing the sacrificial layer from the n-type region;
removing the first mask; and
after the removing of the first mask, forming an n-type work function metal layer around the gate dielectric layer in the n-type region and over the gate dielectric layer and the sacrificial layer in the p-type region.
2. The method of claim 1 , further comprising:
after the forming of the n-type work function metal layer, forming a second mask covering the n-type region and exposing the p-type region;
with the second mask in place, removing the n-type work function metal layer from the p-type region;
with the second mask in place, removing the sacrificial layer from the p-type region;
removing the second mask; and
after the removing of the second mask, forming a p-type work function metal layer over the n-type work function metal layer in the n-type region and around the gate dielectric layer in the p-type region.
3. The method of claim 2 , further comprising:
forming a gate electrode over the p-type work function metal layer in both the n-type region and the p-type region.
4. The method of claim 2 , further comprising:
after the forming of the n-type work function metal layer, forming a passivation layer over the n-type work function metal layer in both the n-type region and the p-type region; and
removing the passivation layer from the p-type region before or concurrently with the removing of the n-type work function metal layer from the p-type region.
5. The method of claim 4 , wherein the passivation layer includes a layer of alumina, a layer of silicon, a layer of silicon dioxide, or a layer of silicon dioxide over a layer of silicon.
6. The method of claim 4 , wherein the passivation layer merges in the space between the second channel layers.
7. The method of claim 1 , wherein the gate dielectric layer includes an interfacial layer and a high-k dielectric layer over the interfacial layer.
8. The method of claim 1 , wherein the sacrificial layer includes alumina, titanium nitride, or silicon oxycarbide.
9. The method of claim 1 , wherein the n-type work function metal layer includes TiAlC, TiAl, TiC, TaAlC, TiSiAlC, or a bi-layer of TiAlC and TiN.
10. A method comprising:
providing a structure having first channel layers in a p-type region and second channel layers in an n-type region;
forming a high-k dielectric layer around the first channel layers and around the second channel layers;
forming a sacrificial layer around the high-k dielectric layer in both the p-type region and the n-type region, wherein the sacrificial layer merges in space between the first channel layers and merges in space between the second channel layers;
etching the sacrificial layer such that only portions of the sacrificial layer in the space between the first channel layers and in the space between the second channel layers remain;
forming a first mask covering the p-type region and exposing the n-type region;
with the first mask in place, removing the sacrificial layer from the n-type region;
removing the first mask;
after the removing of the first mask, forming an n-type work function metal layer around the high-k dielectric layer in the n-type region and over the high-k dielectric layer and the sacrificial layer in the p-type region; and
forming a passivation layer over the n-type work function metal layer in both the n-type region and the p-type region, wherein the passivation layer merges in the space between the second channel layers.
11. The method of claim 10 , wherein the n-type work function metal layer includes TiAlC, TiAl TiC, TaAlC, TiSiAlC, or a bi-layer of TiAlC and TiN.
12. The method of claim 11 , wherein the passivation layer includes a layer of silicon, a layer of silicon dioxide, or a layer of silicon dioxide over a layer of silicon.
13. The method of claim 10 , further comprising:
after the forming of the passivation layer, forming a second mask covering the n-type region and exposing the p-type region;
with the second mask in place, removing the passivation layer, the n-type work function metal layer, and the sacrificial layer from the p-type region;
removing the second mask; and
after the removing of the second mask, forming a p-type work function metal layer over the n-type work function metal layer in the n-type region and around the high-k dielectric layer in the p-type region.
14. The method of claim 10 , wherein the sacrificial layer includes alumina or titanium nitride, or silicon oxycarbide.
15. The method of claim 10 , further comprising:
before the forming of the high-k dielectric layer, forming an interfacial layer around the first channel layers and around the second channel layers, wherein the high-k dielectric layer is formed around the interfacial layer.
16. A device, comprising:
a substrate having a p-type region and an n-type region;
first channel layers over the p-type region and second channel layers over the n-type region;
a gate dielectric layer around the first channel layers and around the second channel layers;
an n-type work function metal layer around the gate dielectric layer that is around the second channel layers, wherein the n-type work function metal layer is not disposed over the gate dielectric layer that is around the first channel layers;
a p-type work function metal layer around the gate dielectric layer that is around the first channel layers and over the n-type work function metal layer; and
a passivation layer between the n-type work function metal layer and the p-type work function metal layer, wherein the passivation layer merges in space between the second channel layers.
17. The device of claim 16 , wherein the passivation layer includes a layer of alumina, a layer of silicon, a layer of silicon dioxide, or a layer of silicon dioxide over a layer of silicon.
18. The device of claim 17 , wherein the passivation layer includes a layer of polysilicon or amorphous silicon.
19. The device of claim 16 , wherein the p-type work function metal layer merges in space between the first channel layers.
20. The device of claim 16 , wherein the passivation layer includes a semiconductor material, a dielectric material, or a bi-layer of a semiconductor material and a dielectric material.