Logic compatible RRAM structure and process

1. A device comprising:

a first metal layer disposed in a substrate;

a first dielectric layer disposed over the substrate;

a first electrode including a first portion disposed directly on the first metal layer and a second portion disposed over the first dielectric layer, the first portion of the first electrode being at a first height and the second portion of the first electrode being at a second height that is different from the first height, wherein the second portion of the first electrode has a first sidewall that faces away from the first portion of the first electrode;

a metal oxide layer including a first portion disposed over the first portion of the first electrode and a second portion disposed over the second portion of the first electrode, wherein the second portion of the metal oxide later has a second sidewall that faces away from the first portion of the metal oxide layer, wherein the first sidewall and the second sidewall are vertically aligned along a first plane; and

a second electrode including a first portion disposed over the first portion of the metal oxide layer and a second portion disposed over the second portion of the metal oxide layer, the first portion of the second electrode being at a third height and the second portion of the second electrode being at a fourth height that is different from the third height and the second height, wherein the second portion of the second electrode has a third sidewall that faces away from the first portion of the second electrode, wherein the third sidewall extends vertically along a second plane that is offset from the first plane, and wherein the first and second planes are substantially perpendicular to a top surface the substrate.

2. The device of claim 1 , wherein the second portion of the first electrode interfaces with the first dielectric layer.

3. The device of claim 1 , wherein the first portion of the metal oxide layer interfaces with the first portion of the first electrode and the second portion of the metal oxide layer interfaces with the second portion of the first electrode.

4. The device of claim 1 , wherein the first portion of the second electrode interfaces with the first portion of the metal oxide layer and the second portion of the second electrode interfaces with the second portion of the metal oxide layer.

5. The device of claim 1 , wherein the second height is greater than the first height, and

wherein the fourth height is greater than the third height.

6. The device of claim 1 , further comprising:

a second dielectric layer including a first portion disposed over the first portion of the second electrode and a second portion disposed over the second portion of the second electrode; and

a third dielectric layer disposed over the second dielectric layer; and

a conductive via extending through the second and third dielectric layers to the first portion of the second electrode.

7. The device of claim 1 , further comprising a dielectric sidewall spacer extending along and interfacing with the third sidewall of the second portion of the second electrode.

8. The device of claim 1 , wherein the first sidewall of the second portion of the first electrode is positioned a first distance away from the first portion of the first electrode, and

wherein the third sidewall of the second portion of the second electrode is positioned a second distance away from the first portion of the second electrode, the second distance being less than the first distance.

9. A device comprising:

a first conductive feature disposed in a substrate;

a first dielectric layer disposed over the substrate;

a first electrode including a first portion disposed directly on the first conductive feature and a second portion disposed over the first dielectric layer, the first portion of the first electrode being at a first height and the second portion of the first electrode being at a second height that is different from the first height;

a resistive layer including a first portion disposed over the first portion of the first electrode and a second portion disposed over the second portion of the first electrode;

a second electrode including a first portion disposed over the first portion of the resistive layer and a second portion disposed over the second portion of the resistive layer, the first portion of the second electrode being at a third height and the second portion of the second electrode being at a fourth height that is different from the third height and the second height;

a second dielectric layer disposed directly on the second electrode;

a conductive via extending through the second dielectric layer to the second electrode, wherein a bottommost surface of the conductive via interfaces with the first portion of the second electrode at the third height; and

a third dielectric layer disposed on and directly contacting the second dielectric layer, the second electrode layer, the resistive layer, the first electrode layer and the first dielectric layer.

10. The device of claim 9 , further comprising:

a second conductive feature disposed in the third dielectric layer, and

wherein the conductive via extends from the second conductive feature through the third dielectric layer and the second dielectric layer to the second electrode.

11. The device of claim 9 , further comprising a logic device electrically coupled to the first conductive feature.

12. The device of claim 9 , wherein the resistive layer includes a metal oxide material selected from the group consisting of NiO, TiO, HfO, ZrO, ZnO, WO 3 , Al 2 O 3 , TaO, MoO and CuO.

13. The device of claim 9 , further comprising a dielectric sidewall spacer extending along and interfacing with a sidewall of the second portion of the second electrode and a sidewall of the second dielectric layer.

14. The device of claim 9 , wherein the second portion of the first electrode has a first sidewall that faces away from the first portion of the first electrode, wherein the first sidewall extends vertically aligned along a first plane, and

wherein the second portion of the second electrode has a second sidewall that faces away from the first portion of the second electrode, wherein the second sidewall extends vertically along a second plane that is offset from the first plane, and wherein the first and second planes are substantially perpendicular to a top surface the substrate.

15. A method comprising:

forming a first material layer on a substrate, the substrate including a first conductive feature;

removing a first portion of the first material layer to expose a portion of the first conductive feature;

forming a first electrode layer on the exposed portion of the first conductive feature and a second portion of the first material layer;

forming an oxide layer on the first electrode layer;

forming a second electrode layer on the oxide layer;

patterning the second electrode layer such that the patterned second electrode layer extends laterally over the substrate by a first distance;

patterning the oxide layer such that the patterned oxide layer extends laterally over the substrate by a second distance beyond the first distance of the patterned second electrode layer; and

forming a conductive via over the patterned second electrode layer that extends to the patterned second electrode layer.

16. The method of claim 15 , wherein the patterning of the oxide layer includes patterning the first electrode layer such that the patterned first electrode layer extends laterally over the substrate by at least the second distance.

17. The method of claim 15 , further comprising forming a second material layer over the second electrode layer prior to patterning the second electrode layer, and

wherein the patterning of the second electrode layer includes patterning the second material layer such that the patterned second material layer extends laterally over the substrate by at least the first distance.

18. The method of claim 17 , further comprising:

forming a third material layer on the patterned second material layer; and

removing a portion of the third material layer and a portion of the patterned second material layer to form a trench that exposes the patterned second electrode layer, and

wherein the forming of the conductive via over the patterned second electrode layer that extends to the patterned second electrode layer includes forming the conducive via in the trench.

19. The method of claim 15 , further comprising forming a sidewall spacer along a sidewall of the patterned second electrode layer.

20. The method of claim 15 , wherein a third portion of the first material layer is removed during the patterning of the oxide layer.