Voltage generation circuit and input buffer including the voltage generation circuit
A voltage generation circuit may include: a first transistor coupled to an internal supply voltage terminal, and configured as a diode-connected transistor; a second transistor coupled to the first transistor and configured as a diode-connected transistor; and a third transistor coupled between the second transistor and a ground voltage terminal, and configured to operate according to a first reference voltage generated based on an external supply voltage. The voltage generation circuit may limit a variation in level of a second reference voltage which is generated through a drain terminal of the second transistor as a threshold voltage of the second transistor rises according to a rise in level of the internal supply voltage.
1. An input buffer comprising:
an amplifier circuit configured to receive an internal supply voltage, and generate an output signal by amplifying an input signal according to a compensation bias voltage and a first reference voltage generated based on an external supply voltage; and
a compensation circuit configured to generate the compensation bias voltage according to a pre-compensation signal generated through a replica circuit configured by replicating the amplifier circuit and a second reference voltage generated by the compensation circuit,
wherein the compensation circuit generates the second reference voltage having a level that is restricted from varying according to a rise in level of the internal supply voltage.
2. The input buffer according to claim 1 , wherein the compensation circuit generates the second reference voltage in inverse proportion to a variation in level of the first reference voltage.
3. The input buffer according to claim 1 , wherein the amplifier circuit comprises:
a current source configured to adjust the amount of current according to the compensation bias voltage; and
a differential pair coupled between the current source and a ground voltage terminal, and configured to generate the output signal by amplifying the input signal.
4. The input buffer according to claim 1 , wherein the compensation circuit comprises:
a differential amplifier configured to generate the compensation bias voltage by comparing the pre-compensation signal and the second reference voltage; and
a voltage generation circuit configured to generate the second reference voltage which has a change less sensitive to a variation in the internal supply voltage than that in the external supply voltage, according to the internal supply voltage and the first reference voltage.
5. The input buffer according to claim 4 , wherein the voltage generation circuit comprises:
a first transistor configured to receive the internal supply voltage, and configured as a diode-connected transistor;
a second transistor coupled to the first transistor and configured as a diode-connected transistor; and
a third transistor coupled between the second transistor and a ground voltage terminal, and configured to operate according to the first reference voltage,
wherein the voltage generation circuit limits a variation in level of the second reference voltage which is generated through a drain terminal of the second transistor as a threshold voltage of the second transistor rises according to a rise in level of the internal supply voltage.
6. The input buffer according to claim 5 , wherein the internal supply voltage is applied to a bulk terminal of at least one of the first and second transistors.
7. The input buffer according to claim 5 , further comprising a fourth transistor coupled between the third transistor and the ground voltage terminal.
8. The input buffer according to claim 7 , wherein the fourth transistor is configured as a diode-connected transistor.
9. The input buffer according to claim 7 , wherein the ground voltage is applied to a bulk terminal of the fourth transistor.