IP Library › Granted Patent US 11,393,918
Granted Patent B2
US 11,393,918 · App. 17/070,349 · Granted Jul 19, 2022

Semiconductor device and method for manufacturing semiconductor device

Inventors: Shunpei Yamazaki (Tokyo, JP); Kenichi Okazaki (Tochigi, JP); Junichi Koezuka (Tochigi, JP); Toshinari Sasaki (Tokyo, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/66969H01L21/0217H01L21/441H01L29/7869H01L29/78618H01L29/78621H01L29/78693
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Quick Facts
Patent No.
US 11,393,918
App. No.
17/070,349
Granted
Jul 19, 2022
Kind
B2
Abstract

In a top-gate transistor in which an oxide semiconductor film, a gate insulating film, a gate electrode layer, and a silicon nitride film are stacked in this order and the oxide semiconductor film includes a channel formation region, nitrogen is added to regions of part of the oxide semiconductor film and the regions become low-resistance regions by forming a silicon nitride film over and in contact with the oxide semiconductor film. A source and drain electrode layers are in contact with the low-resistance regions. A region of the oxide semiconductor film, which does not contact the silicon nitride film (that is, a region overlapping with the gate insulating film and the gate electrode layer) becomes the channel formation region.

Claims (32)

1. A semiconductor device comprising:

an oxide semiconductor film over a substrate;

a gate insulating film over the oxide semiconductor film;

a gate electrode layer over the gate insulating film;

a first insulating film over the gate electrode layer;

a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor film; and

an interlayer insulating film over the oxide semiconductor film,

wherein top surfaces of the first insulating film, the source electrode layer, the drain electrode layer, and the interlayer insulating film are substantially aligned with each other.

2. The semiconductor device according to claim 1 , wherein the first insulating film is in contact with a top surface of the gate electrode layer.

3. The semiconductor device according to claim 1 , wherein the source electrode layer and the drain electrode layer are over and in contact with a first end portion and a second end portion of the oxide semiconductor film, respectively.

4. The semiconductor device according to claim 1 , wherein the oxide semiconductor film comprises indium, gallium, and zinc.

5. The semiconductor device according to claim 1 ,

wherein the oxide semiconductor film comprises a first region below the source electrode layer, a second region below the drain electrode layer, a third region including a channel, a fourth region between the first region and the third region, and a fifth region between the second region and the third region, and

wherein resistance of the first region and the second region is lower than resistance of the fourth region and the fifth region.

6. The semiconductor device according to claim 1 , wherein the gate electrode layer comprises a same material as the source electrode layer and the drain electrode layer.

7. A semiconductor device comprising:

an oxide semiconductor film over a substrate;

a gate insulating film over the oxide semiconductor film;

a gate electrode layer over the gate insulating film;

a first insulating film over the gate electrode layer;

a first sidewall insulating film and a second sidewall insulating film in contact with a first side surface and a second side surface of the gate electrode layer, respectively;

a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor film; and

an interlayer insulating film over the oxide semiconductor film,

wherein the gate electrode layer is surrounded by the first sidewall insulating film, the second sidewall insulating film, the first insulating film, and the gate insulating film, and

wherein top surfaces of the first insulating film, the source electrode layer, the drain electrode layer, and the interlayer insulating film are substantially aligned with each other.

8. The semiconductor device according to claim 7 , wherein the first insulating film is in contact with a top surface of the gate electrode layer.

9. The semiconductor device according to claim 7 , wherein the source electrode layer and the drain electrode layer are over and in contact with a first end portion and a second end portion of the oxide semiconductor film, respectively.

10. The semiconductor device according to claim 7 , wherein the oxide semiconductor film comprises indium, gallium, and zinc.

11. The semiconductor device according to claim 7 ,

wherein the oxide semiconductor film comprises a first region below the source electrode layer, a second region below the drain electrode layer, a third region including a channel, a fourth region between the first region and the third region, and a fifth region between the second region and the third region, and

wherein resistance of the first region and the second region is lower than resistance of the fourth region and the fifth region.

12. The semiconductor device according to claim 7 , wherein the gate electrode layer comprises a same material as the source electrode layer and the drain electrode layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 14, 2020
From: YAMAZAKI, SHUNPEI; OKAZAKI, KENICHI; KOEZUKA, JUNICHI; SASAKI, TOSHINARI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 054053/0583 →
Priority Claims (1)
JP 2012-147633 · Jun 29, 2012 · national
Continuity (3)
Continuation 15292243 · Oct 13, 2016
Division 13924757 · Jun 24, 2013
Related Publication 20210184021A1 · Jun 17, 2021
Cited By (2)
US 12,677,446 US 12,717,431