System and methods for hardware-software cooperative pipeline error detection
An error reporting system utilizes a parity checker to receive data results from execution of an original instruction and a parity bit for the data. A decoder receives an error correcting code (ECC) for data resulting from execution of a shadow instruction of the original instruction, and data error correction is initiated on the original instruction result on condition of a mismatch between the parity bit and the original instruction result, and the decoder asserting a correctable error in the original instruction result.
1. An error reporting system for a computer processor, the error reporting system comprising:
a parity checker configured to receive data bits (D 1 ) resulting from execution of an original instruction by the computer processor, the parity checker further configured to receive a parity bit for D 1 ;
a decoder configured to receive an error correcting code (ECC) for data bits (D 2 ) resulting from execution by the computer processor of a shadow instruction of the original instruction; and
logic to initiate a data error correction on D 1 on condition of (a) a mismatch between the parity bit and D 1 , and (b) the decoder asserting a correctable error in D 1 based on the ECC for D 2 .
2. The error reporting system of claim 1 , the logic comprising an AND gate configured to receive an output of the parity checker and to receive a correctable error signal output (CE) of the decoder.
3. The error reporting system of claim 2 , the logic comprising an INVERT-AND-OR (IAO) cell configured to receive the output of the parity checker, the correctable error signal output CE of the decoder, and a detected-uncorrectable signal output (DUE) of the decoder.
4. A method comprising:
executing an original instruction;
executing a shadow instruction of the original instruction;
generating a data bits D 1 from execution of the original instruction;
generating a parity bit for D 1 ;
generating a data bits D 2 from execution of the shadow instruction;
generating an error correcting code (an ECC) for D 2 ; and
initiating a data error correction on D 1 on condition that a parity checker detects a mismatch between the parity bit and D 1 , and a decoder asserts that the ECC indicates a correctable error in D 1 .
5. The method of claim 4 , further comprising:
writing D 1 to a first memory bank; and
writing the ECC and the parity bit to a second memory bank different than the first memory bank.
6. The method of claim 5 , further comprising:
storing four data bits in a first row of the first memory bank; and
storing 16 ECCs and 16 parity bits in a first row of the second memory bank.
7. The method of claim 4 , wherein D 1 is 32 bits and ECC is 7 bits.
8. The method of claim 4 , further comprising:
ANDing a parity check signal and an ECC decoder correctable error signal (CE) to generate an indication of a correctable error in D 1 .
9. The method of claim 8 , further comprising:
asserting a detected-uncorrectable-error on condition that the parity check signal is asserted and CE is not asserted.
10. The method of claim 9 , further comprising:
also asserting the detected-uncorrectable-error on condition that the decoder indicates a detectable-uncorrectable error.
11. A computer system comprising:
a processor; and
an error checker for the processor configured to initiate a data error correction (DEC) for first data bits (D 1 ) resulting from execution of an original instruction by the processor, the DEC initiated on condition of a mismatch between D 1 and a parity bit for D 1 ; and
a decoder configured to receive an error correcting code (ECC) for second data bits (D 2 ) resulting from execution of a shadow instruction of the original instruction by the processor, and to assert a correctable error (CE) signal in D 1 based on the ECC for D 2 .
12. The computer system of claim 11 , comprising an AND gate configured to receive an output of the error checker and to receive the CE signal.
13. The computer system of claim 12 , comprising an INVERT-AND-OR (IAO) cell configured to receive (a) the output of the error checker, (b) the CE signal, and (c) a detected-uncorrectable signal output (DUE) of the decoder.
14. A data processor comprising:
a decoder;
a parity checker; and
logic to initiate a data correction on first data bits D 1 generated by the data processor as a result of executing an original instruction, the data correction initiated on condition that (a) the parity checker detects a parity error for D 1 , and (b) an error correcting code generated by the data processor for second data bits D 2 as a result of executing a shadow instruction of the original instruction indicates a correctable error in D 1 .
15. The data processor of claim 14 , wherein D 1 is 32 bits and the error correcting code is 7 bits.
16. The data processor of claim 14 , further comprising:
a circuit to AND (a) the parity error, and (b) a correctable error signal (CE) resulting from decoding the error correcting code, to generate an indication of a correctable error in D 1 .