Semiconductor structure and manufacturing method thereof
View Patent ↗A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an integrated circuit (IC) component, an insulating layer laterally encapsulating sidewalls of the IC component, a redistribution structure disposed on the insulating layer and the IC component, and a warpage control portion coupling to a back side of the IC component opposite to the redistribution structure. The redistribution structure is electrically connected to the IC component. The warpage control portion includes a substrate, a patterned dielectric layer disposed between the substrate and the IC component, and a metal pattern embedded in the patterned dielectric layer and electrically isolated from the IC component.
1. A semiconductor structure, comprising:
an integrated circuit (IC) portion comprising:
an IC component embedded in an insulating layer; and
a redistribution structure disposed on the IC component and the insulating layer, wherein a bonding connector of the IC component is bonded to a bonding connector of the redistribution structure, and a contact area of the bonding connector of the IC component at a bonding interface of the IC component and the redistribution structure is substantially equal to a surface area of the bonding connector of the redistribution structure; and
a warpage control portion attached to the IC portion and comprising:
a first substrate; and
a first metal pattern embedded in a first dielectric layer and interposed between the first substrate and the IC portion, wherein the first metal pattern is electrically floating in the warpage control portion.
2. The semiconductor structure of claim 1 , further comprising:
a bonding layer interposed between the warpage control portion and the IC portion.
3. The semiconductor structure of claim 1 , wherein the first metal pattern is substantially leveled with the first dielectric layer.
4. The semiconductor structure of claim 1 , wherein sidewalls of the redistribution structure, the insulating layer, the first substrate, and the first dielectric layer are substantially leveled with one another.
5. The semiconductor structure of claim 1 , wherein the first metal pattern of the warpage control portion is located within a distribution region that overlaps an orthographic projection area of the IC component, and the first metal pattern of the warpage control portion is electrically isolated.
6. The semiconductor structure of claim 1 , wherein the first metal pattern of the warpage control portion comprises:
first features and second features, wherein the first features are distributed within a distribution region that overlaps an orthographic projection area of the IC component, and the second features are distributed outside the distribution region and have a pattern distribution density denser than that of the first features.
7. The semiconductor structure of claim 1 , wherein the first metal pattern of the warpage control portion comprises:
first features and second features, wherein the first features are distributed within a distribution region that overlaps an orthographic projection area of the IC component, the second features are distributed outside the distribution region and have a pattern distribution density sparser than that of the first features.
8. The semiconductor structure of claim 1 , wherein the warpage control portion further comprises:
a second substrate;
a second metal pattern embedded in a second dielectric layer and interposed between the first substrate and the second substrate; and
a bonding layer coupling the second dielectric layer and the second metal pattern to the first substrate.
9. A semiconductor structure, comprising:
an integrated circuit (IC) portion comprising:
an IC component embedded in an insulating layer; and
a redistribution structure bonded to the IC component and the insulating layer, the redistribution structure being electrically connected to the IC component, wherein the redistribution structure comprises bonding connectors and a bonding dielectric layer covering the bonding connectors, and the bonding connectors and the bonding dielectric layer at a bonding surface of the redistribution structure are substantially leveled with one another;
a warpage control portion attached to the IC portion and comprising:
a supporting substrate;
a metal pattern embedded in a dielectric layer and interposed between the supporting substrate and the IC portion, wherein the metal pattern is electrically floating in the warpage control portion; and
a bonding layer overlying the dielectric layer and the metal pattern and attached to the IC portion.
10. The semiconductor structure of claim 9 , wherein the metal pattern of the warpage control portion is located within a distribution region that overlaps an orthographic projection area of the IC component.
11. The semiconductor structure of claim 9 , wherein sidewalls of the redistribution structure, the insulating layer, the bonding layer, the supporting substrate, and the dielectric layer are substantially leveled with one another.
12. The semiconductor structure of claim 9 , wherein the metal pattern of the warpage control portion comprises:
first features and second features, wherein the first features are distributed within a distribution region that overlaps an orthographic projection area of the IC component, and the second features are distributed outside the distribution region and have a pattern distribution density different from that of the first features.
13. A semiconductor structure, comprising:
an integrated circuit (IC) portion comprising:
an IC component;
an insulating layer covering the IC component;
a redistribution structure overlying the insulating layer and the IC component, the redistribution structure being electrically connected to the IC component, wherein a contact area of a bonding connector of the IC component at a bonding interface of the IC component and the redistribution structure substantially matches a surface area of a bonding connector of the redistribution structure; and
a warpage control portion underlying the IC portion and comprising:
a supporting substrate;
a metal pattern disposed between the IC portion and the supporting substrate, the metal pattern being electrically floating in the warpage control portion; and
a patterned dielectric layer overlying the supporting substrate, and the patterned dielectric layer covering and being substantially leveled with the metal pattern.
14. The semiconductor structure of claim 13 , further comprising:
a bonding layer coupling the warpage control portion to the IC portion.
15. The semiconductor structure of claim 13 , wherein the warpage control portion further comprises:
an oxide layer interposed between the supporting substrate and the patterned dielectric layer.
16. The semiconductor structure of claim 13 , wherein the metal pattern of the warpage control portion is located within a distribution region that underlies a region of the IC component, and the metal pattern of the warpage control portion comprises an alignment feature disposed in a border region surrounding the distribution region.
17. The semiconductor structure of claim 13 , wherein at the bonding interface, the bonding connector of the IC component is bonded to the bonding connector of the redistribution structure, and a bonding dielectric layer of the IC component laterally covering the bonding connector of the IC component is bonded to a bonding dielectric layer of the redistribution structure laterally covering the bonding connector of the redistribution structure.
18. The semiconductor structure of claim 13 , wherein the metal pattern of the warpage control portion comprises:
a plurality of first features distributed within a first region that underlies a region of the IC component; and
a plurality of second features distributed within a second region that underlies a region of the insulating layer, wherein a pattern distribution density of the plurality of first features is sparser than the plurality of second features.
19. The semiconductor structure of claim 13 , wherein the metal pattern of the warpage control portion comprises:
a plurality of first features distributed within a first region that underlies a region of the IC component; and
a plurality of second features distributed within a second region that underlies a region of the insulating layer, wherein a pattern distribution density of the plurality of first features is denser than the plurality of second features.
20. The semiconductor structure of claim 13 , wherein the warpage control portion further comprises:
an additional supporting substrate;
an additional patterned dielectric layer disposed between the supporting substrate and the additional supporting substrate;
an additional metal pattern embedded in the additional patterned dielectric layer, wherein the additional metal pattern is electrically floating in the warpage control portion.