FinFET device and method of forming

1. A method comprising:

forming a first source/drain contact opening in an insulating layer, the insulating layer covering a first semiconductor structure and a second semiconductor structure, the first semiconductor structure and the second semiconductor structure extending parallel to a first horizontal direction, the first semiconductor structure and the second semiconductor structure extending over a substrate in a vertical direction, wherein the first source/drain contact opening comprises:

a first deep portion formed directly over the first semiconductor structure; and

a first shallow portion extending from the first deep portion in a second horizontal direction toward the second semiconductor structure at least to a point halfway between the first semiconductor structure and the second semiconductor structure, the second horizontal direction being perpendicular to the first horizontal direction; and

forming a first source/drain contact in the first source/drain contact opening.

2. The method of claim 1 , further comprising forming an interconnect structure over the first source/drain contact and the insulating layer.

3. The method of claim 1 , further comprising forming a protection layer over the first source/drain contact.

4. The method of claim 1 , wherein forming the first source/drain contact opening comprises:

etching the insulating layer above the first semiconductor structure to form an opening;

filling, at least partially, the opening with a fill material;

etching the insulating layer selectively to the fill material to form a second opening; and

removing the fill material by etching the fill material selectively to the insulating layer.

5. The method of claim 1 , further comprising forming a gate structure between the first semiconductor structure and the second semiconductor structure, the insulating layer surrounding the gate structure.

6. The method of claim 5 , wherein the first source/drain contact is formed in physical contact with a gate dielectric layer and a gate electrode of the gate structure.

7. The method of claim 5 , further comprising a spacer layer adjacent the gate structure, wherein forming the first source/drain contact opening exposes portions of the spacer layer.

8. The method of claim 7 , wherein forming the gate structure comprises:

forming a sacrificial gate structure; and

replacing the sacrificial gate structure with the gate structure.

9. The method of claim 1 , wherein forming the first source/drain contact comprises forming a barrier layer in the first source/drain contact opening.

10. The method of claim 9 , wherein forming the first source/drain contact further comprises:

forming a metallic material over the barrier layer; and

planarizing the barrier layer and the metallic material.

11. The method of claim 1 , wherein the first semiconductor structure and the second semiconductor structure comprise epitaxial source/drain regions.

12. A method comprising:

forming a fin over a semiconductor substrate;

forming a gate structure over the fin;

forming a first source/drain region in the fin;

depositing an insulating layer over the gate structure;

etching the insulating layer to form a first opening in the insulating layer;

depositing a fill material in the first opening;

patterning the fill material;

etching the insulating layer using the fill material as a mask to form a second opening in the insulating layer;

removing the fill material; and

depositing a source/drain contact in the first opening and the second opening, the source/drain contact comprising a first horizontal bottom surface in contact with the first source/drain region and a second horizontal bottom surface disposed above the first bottom horizontal surface of the first source/drain region and extending in a direction toward a second source/drain region.

13. The method of claim 12 , wherein the second horizontal bottom surface extends at least halfway between the first source/drain region and the second source/drain region.

14. The method of claim 12 , further comprising:

replacing the gate structure with a replacement gate structure; and

after replacing the gate structure, forming an interconnect structure over the insulating layer and the source/drain contact.

15. The method of claim 12 , wherein the second bottom horizontal surface contacts a gate dielectric layer and a gate electrode of the gate structure.

16. A method comprising:

forming a plurality of fins over a substrate;

forming a gate structure over the plurality of fins;

forming a first source/drain region and a second source/drain region in the fins adjacent the gate structure;

depositing an insulating layer over the first source/drain region, the second source/drain region, and the gate structure;

forming a first patterned photoresist over the insulating layer;

patterning the insulating layer to form a first opening using the first patterned photoresist as a first mask;

forming a fill material in the first opening;

forming a second patterned photoresist over the fill material;

patterning the fill material to form a patterned fill material using the second patterned photoresist as a second mask;

patterning the insulating layer to form a second opening using the patterned fill material as a third mask; and

forming a first source/drain contact in the first opening and the second opening, wherein the first source/drain contact comprises a first horizontal bottom surface directly adjacent the first source/drain region, wherein the first source/drain contact comprises a first side surface extending from the first horizontal bottom surface to a second horizontal bottom surface, the second horizontal bottom surface being disposed vertically between the first horizontal bottom surface and a top surface of the insulating layer, the second horizontal bottom surface extending from the first side surface to a point halfway between the first source/drain region and the second source/drain region.

17. The method of claim 16 , wherein forming the first source/drain contact comprises:

depositing a first contact layer in the first opening and the second opening; and

depositing a metallic material over the first contact layer.

18. The method of claim 16 , wherein the second horizontal bottom surface is directly adjacent the gate structure.

19. The method of claim 16 , further comprising forming a first spacer on a first side of the gate structure and a second spacer on a second side of the gate structure opposite the first side, wherein the second horizontal bottom surface contacts a top surface of the first spacer, wherein a top surface of the second spacer is covered by the insulating layer.

20. The method of claim 16 , further comprising forming an interconnect structure over the insulating layer and the first source/drain contact.