Semiconductor packages having a dam structure
A semiconductor package is disclosed. The disclosed semiconductor package includes a substrate having bonding pads at an upper surface thereof, a lower semiconductor chip, at least one upper semiconductor chip disposed on the lower semiconductor chip, and a dam structure having a closed loop shape surrounding the lower semiconductor chip. The dam structure includes narrow and wide dams disposed between the lower semiconductor chip and the bonding pads. The wide dam has a greater inner width than the narrow dam. The semiconductor packages further includes an underfill disposed inside the dam structure and being filled between the substrate and the lower semiconductor chip.
1. A semiconductor package comprising:
a substrate having bonding pads at an upper surface thereof;
a lower semiconductor chip disposed on the substrate and at least one upper semiconductor chip attached to an adhesive in contact with an upper surface of the lower semiconductor chip;
a dam structure disposed on the substrate and having a single closed loop shape surrounding the lower semiconductor chip, the dam structure including narrow and wide dams connected to one another to form the single closed loop shape, the narrow dam being disposed between the lower semiconductor chip and the bonding pads, and the wide dam having a greater inner width than the narrow dam; and
an underfill disposed inside the dam structure and being filled between the substrate and the lower semiconductor chip,
wherein the narrow dam includes a linear segment adjacent to a first side surface of the lower semiconductor chip,
wherein the wide dam includes a linear segment adjacent to the first side surface of the lower semiconductor chip,
wherein at least one of the bonding pads includes a first surface adjacent to the first side surface of the lower semiconductor chip and a second surface opposite to the first surface, and
wherein the linear segment of the wide dam is farther from the first side surface of the lower semiconductor chip than the first surface of the at least one of the bonding pads.
2. The semiconductor package according to claim 1 , wherein a distance between the lower semiconductor chip and the wide dam is greater than a distance between the lower semiconductor chip and the narrow dam.
3. The semiconductor package according to claim 1 , wherein a distance between the lower semiconductor chip and the narrow dam is smaller than a distance between the lower semiconductor chip and each of the bonding pads.
4. The semiconductor package according to claim 1 , wherein:
the lower semiconductor chip is electrically connected to the substrate through bumps; and
the upper semiconductor chip is electrically connected to the substrate through bonding wires.
5. The semiconductor package according to claim 1 , wherein, when viewed in a plan view:
the narrow dam surrounds the first side surface and second and third side surfaces of the lower semiconductor chip;
the wide dam surrounds the first and third surfaces of the lower semiconductor chip and a fourth surface of the lower semiconductor chip;
the dam structure further includes a first connector connecting a first end of the narrow dam and a first end of the wide dam; and
the dam structure further includes a second connector connecting a second end of the narrow dam and a second end of the wide dam.
6. The semiconductor package according to claim 5 , wherein a distance between each of the first and second connectors and a bonding pad disposed adjacent thereto is 50 to 150 μm.
7. The semiconductor package according to claim 5 , wherein the bonding pads are disposed to face corresponding ones of the first to third side surfaces of the lower semiconductor chip.
8. The semiconductor package according to claim 1 , wherein a distance between the narrow dam and each of the bonding pads is 50 to 150 μm.
9. The semiconductor package according to claim 1 , wherein a distance between the wide dam and each adjacent side surface of the substrate is 100 to 300 μm.
10. The semiconductor package according to claim 1 , wherein a distance between the lower semiconductor chip and the narrow dam is 200 to 400 μm.
11. The semiconductor package according to claim 1 , wherein a distance between the lower semiconductor chip and the wide dam is 500 to 1,000 μm.
12. The semiconductor package according to claim 1 , wherein the dam structure has a height of 18 μm or less.
13. The semiconductor package according to claim 1 , further comprising:
an alignment mark disposed on the substrate,
wherein the dam structure includes a cut-out bent at a right angle to face the alignment mark.
14. The semiconductor package according to claim 1 , wherein:
the at least one upper semiconductor chip includes a first upper semiconductor chip and a second upper semiconductor chip; and
the narrow dam includes a first narrow dam disposed between the first upper semiconductor chip and first bonding pads of the bonding pads, and a second narrow dam disposed between the second upper semiconductor chip and second bonding pads of the bonding pads, and the wide dam is disposed between the first narrow dam and the second narrow dam.
15. A semiconductor package comprising:
a substrate having bonding pads at an upper surface thereof;
a lower semiconductor chip mounted on the substrate by flip-chip bonding and an upper semiconductor chip mounted on the lower semiconductor chip by wire bonding, the upper semiconductor chip attached to an adhesive in contact with an upper surface of the lower semiconductor chip;
an external connection terminal disposed below the substrate;
a dam structure disposed on the substrate and having a single closed loop shape surrounding the lower semiconductor chip, the dam structure including narrow and wide dams connected to one another to form the single closed loop shape, the narrow dam being disposed between the lower semiconductor chip and the bonding pads, and the wide dam having a greater inner width than the narrow dam;
an underfill disposed inside the dam structure and being filled between the substrate and the lower semiconductor chip; and
an encapsulant covering the substrate, the lower semiconductor chip, and the upper semiconductor chip,
wherein the narrow dam includes a linear segment adjacent to a first side surface of the lower semiconductor chip,
wherein the wide dam includes a linear segment adjacent to the first side surface of the lower semiconductor chip,
wherein at least one of the bonding pads includes a first surface adjacent to the first side surface of the lower semiconductor chip and a second surface opposite to the first surface, and
wherein the linear segment of the wide dam is farther from the first side surface of the lower semiconductor chip than the first surface of the at least one of the bonding pads.
16. A semiconductor package comprising:
a substrate having bonding pads at an upper surface thereof;
a lower semiconductor chip mounted on the substrate by flip-chip bonding and an upper semiconductor chip mounted on the lower semiconductor chip by wire bonding;
an external connection terminal disposed below the substrate;
a dam structure disposed on the substrate and having a closed loop shape surrounding the lower semiconductor chip, the dam structure including narrow and wide dams, the narrow dam being disposed between the lower semiconductor chip and the bonding pads;
an underfill disposed inside the dam structure and being filled between the substrate and the lower semiconductor chip; and
an encapsulant covering the substrate, the lower semiconductor chip, and the upper semiconductor chip,
wherein the underfill directly contacts inner surfaces of the narrow and wide dams,
wherein the narrow dam includes a first linear segment adjacent to a first side surface of the lower semiconductor chip, a second linear segment adjacent to a second side surface of the lower semiconductor chip, and a third linear segment adjacent to a third side surface of the lower semiconductor chip,
wherein the wide dam includes a first linear segment adjacent to the first side surface of the lower semiconductor chip, a second linear segment adjacent to a fourth side surface of the lower semiconductor chip, and a third linear segment adjacent to the third side surface of the lower semiconductor chip,
wherein the second linear segment of the narrow dam is a single continuous line segment having a length that is greater than a length of the second side surface of the lower semiconductor chip,
wherein the second linear segment of the wide dam is a single continuous line segment having a length that is greater than a length of the fourth side surface of the lower semiconductor chip, and
wherein a distance between the first linear segment of the narrow dam and the first side surface of the lower semiconductor chip is less than a distance between the first linear segment of the wide dam and the first side surface of the lower semiconductor chip.
17. The semiconductor package of claim 16 , wherein a distance between the third linear segment of the narrow dam and the third side surface of the lower semiconductor chip is less than a distance between the third linear segment of the wide dam and the third side surface of the lower semiconductor chip.
18. The semiconductor package of claim 16 , wherein a distance between the second linear segment of the narrow dam and the second side surface of the lower semiconductor chip is less than a distance between the second linear segment of the wide dam and the fourth side surface of the lower semiconductor chip.
19. The semiconductor package of claim 16 , wherein the narrow and wide dams are connected to one another.