Chip package structure
A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a first bump and a first dummy bump between the chip and the substrate. The first bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, the first dummy bump is between the first bump and a corner of the chip, and the first dummy bump is wider than the first bump.
1. A chip package structure, comprising:
a substrate;
a chip over the substrate;
a first bump and a first dummy bump between the chip and the substrate, wherein the first bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, the first dummy bump is between the first bump and a corner of the chip, and the first dummy bump is wider than the first bump;
a dummy solder layer between the first dummy bump and the substrate; and
a solder ball between the first bump and the substrate, wherein a first bottom surface of the dummy solder layer is higher than a second bottom surface of the solder ball.
2. The chip package structure as claimed in claim 1 , wherein the first dummy bump has a first strip portion and a second strip portion, and the first strip portion is not parallel to the second strip portion.
3. The chip package structure as claimed in claim 2 , wherein the chip has a first edge and a second edge, the first edge and the second edge meet at the corner of the chip, and the first strip portion is substantially parallel to the first edge.
4. The chip package structure as claimed in claim 3 , wherein the second strip portion is substantially parallel to the second edge.
5. The chip package structure as claimed in claim 1 , further comprising:
an underfill layer between the chip and the substrate and between the first dummy bump and the substrate.
6. The chip package structure as claimed in claim 1 , further comprising:
a second bump between the first bump and the substrate; and
a second dummy bump between the chip and the substrate, wherein the second dummy bump is connected to the substrate and electrically insulated from the chip, and the second dummy bump is wider than the second bump and close to the corner of the chip.
7. The chip package structure as claimed in claim 6 , wherein the second dummy bump is wider than the first bump.
8. The chip package structure as claimed in claim 6 , further comprising:
an underfill layer between the chip and the substrate and between the chip and the second dummy bump.
9. The chip package structure as claimed in claim 8 , wherein the underfill layer is further between the first dummy bump and the second dummy bump.
10. A chip package structure, comprising:
a first substrate;
a chip over a first surface of the first substrate; and
a bump and a dummy bump over a second surface of the first substrate, wherein the bump is electrically connected to the chip, the dummy bump is electrically insulated from the chip, the dummy bump is between the bump and a corner of the first substrate, and the dummy bump is a strip structure.
11. The chip package structure as claimed in claim 10 , wherein the dummy bump is wider than the bump.
12. The chip package structure as claimed in claim 10 , wherein the dummy bump has a first strip portion and a second strip portion, and the first strip portion is not parallel to the second strip portion.
13. The chip package structure as claimed in claim 10 , further comprising:
a second substrate, wherein the first substrate is over the second substrate, the bump connects the first substrate to the second substrate, and the dummy bump is electrically insulated from the second substrate.
14. The chip package structure as claimed in claim 13 , further comprising:
a protective layer between the first substrate and the second substrate, wherein the protective layer surrounds the dummy bump and the bump, and the protective layer is partially between the dummy bump and the second substrate.
15. The chip package structure as claimed in claim 14 , wherein the first substrate comprises a redistribution structure, the protective layer has a protruding portion extending into the redistribution structure, and the protruding portion is close to the corner of the first substrate.
16. The chip package structure as claimed in claim 15 , wherein the protruding portion is between the bump and the corner of the first substrate.
17. The chip package structure as claimed in claim 15 , wherein the protruding portion is between the dummy bump and the bump.
18. A chip package structure, comprising:
a package comprising a first substrate and a chip over the first substrate; and
a second substrate, wherein the package is over and bonded to the second substrate, wherein the second substrate comprises a redistribution structure, the redistribution structure comprises a dielectric structure, a wiring layer, and a dummy structure in the dielectric structure, the wiring layer is electrically connected to the package, the dummy structure is electrically insulated from the package, the wiring layer and the dummy structure are made of a same material, and the dummy structure overlaps a corner of the package.
19. The chip package structure as claimed in claim 18 , wherein the package has a first edge and a second edge, the first edge and the second edge meet at the corner of the package, the dummy structure has a first strip portion and a second strip portion, and the first strip portion overlaps the first edge.
20. The chip package structure as claimed in claim 19 , wherein the second strip portion overlaps the second edge.