Semiconductor package
Some embodiments of the present disclosure provide a semiconductor package including: a package substrate including a main pad and a main wiring pattern; a semiconductor chip on the package substrate; a plurality of connection bumps between the package substrate and the semiconductor chip and including a plurality of connection solder patterns on the main pad and a plurality of connection pillars on the connection solder patterns; a dummy insulating pattern between the package substrate and the semiconductor chip and configured to cover the main wiring pattern; and a plurality of dummy pillars on the dummy insulating pattern, wherein the dummy pillars are in contact with the dummy insulating pattern, and are electrically insulated from the dummy insulating pattern.
1 . A semiconductor package comprising:
a package substrate including a main pad and a main wiring pattern;
a semiconductor chip on the package substrate;
a plurality of connection bumps between the package substrate and the semiconductor chip and including a plurality of connection solder patterns on the main pad and a plurality of connection pillars on the connection solder patterns;
a dummy insulating pattern between the package substrate and the semiconductor chip and configured to cover the main wiring pattern; and
a plurality of dummy pillars on the dummy insulating pattern,
wherein the dummy pillars are in contact with the dummy insulating pattern, and are electrically insulated from the dummy insulating pattern.
2 . The semiconductor package of claim 1 , wherein
a thickness of the dummy pillars is the same as a thickness of the connection pillars.
3 . The semiconductor package of claim 2 , wherein
a sum of the thickness of the dummy pillars and a thickness of the dummy insulating pattern is equal to a thickness of the connection bumps.
4 . The semiconductor package of claim 1 , wherein
the main pad extends from an upper surface of the package substrate, and
an upper surface of the main wiring pattern is coplanar with the upper surface of the package substrate.
5 . The semiconductor package of claim 1 , wherein
a distance between the dummy pillars closest to each other is equal to a distance between the connection pillars closest to each other.
6 . The semiconductor package of claim 4 , wherein
a diameter of the dummy pillars is the same as a diameter of the connection pillars.
7 . The semiconductor package of claim 1 , wherein
the dummy insulating pattern does not vertically overlap the main pad.
8 . The semiconductor package of claim 7 , wherein
a width of the dummy insulating pattern is greater than a width of the dummy pillars.
9 . The semiconductor package of claim 7 , wherein
the dummy insulating pattern is in contact with the connection solder patterns.
10 . The semiconductor package of claim 1 , wherein
the main wiring pattern vertically overlaps a portion of the dummy pillars.
11 . The semiconductor package of claim 1 , wherein
the dummy pillars and the connection pillars include a same material.
12 . The semiconductor package of claim 1 , further comprising
a chip pad at a lower surface of the semiconductor chip that is physically and electrically connected to the connection pillars,
wherein the chip pad does not vertically overlap the dummy pillars.
13 . A semiconductor package comprising:
a package substrate;
a semiconductor chip on the package substrate;
a plurality of connection bumps between the package substrate and the semiconductor chip, each including a connection solder pattern and a connection pillar on the connection solder pattern;
a dummy insulating pattern between the package substrate and the semiconductor chip and positioned between the connection bumps; and
a plurality of dummy pillars on the dummy insulating pattern,
wherein the dummy pillars are in contact with the dummy insulating pattern, and are electrically insulated from the dummy insulating pattern.
14 . The semiconductor package of claim 13 , wherein
a thickness of the dummy pillars is the same as a thickness of the connection pillar, and a thickness of the dummy insulating pattern is the same as a thickness of the connection solder pattern.
15 . A semiconductor package comprising:
a package substrate including a main pad and a main wiring pattern;
a semiconductor chip on the package substrate and including a chip pad;
a plurality of connection bumps between the package substrate and the semiconductor chip;
a dummy insulating pattern between the package substrate and the semiconductor chip and configured to cover the main wiring pattern; and
a plurality of dummy pillars on the dummy insulating pattern,
wherein the plurality of connection bumps include:
a plurality of connection solder patterns on the main pad; and
a plurality of connection pillars on the connection solder patterns and connected to the chip pad, and
a thickness of the dummy pillars is the same as a thickness of the connection pillars.
16 . The semiconductor package of claim 15 , wherein
the dummy insulating pattern is between the connection bumps.
17 . The semiconductor package of claim 16 , wherein
the dummy pillars vertically overlap the dummy insulating pattern.
18 . The semiconductor package of claim 15 , wherein
each of the dummy pillars is in contact with the dummy insulating pattern, and is electrically insulated from the dummy insulating pattern.
19 . The semiconductor package of claim 15 , wherein
a distance between the dummy pillars closest to each other is equal to a distance between the connection pillars closest to each other.
20 . The semiconductor package of claim 19 , wherein
a distance between the dummy pillars closest to each other is equal to a distance between the connection pillars closest to the dummy pillars.