Hybrid memristor/field-effect transistor memory cell and its information encoding scheme

1. A resistive random-access memory (ReRAM) comprising a hybrid memory cell, wherein the hybrid memory cell comprises:

a left resistance-switching device comprising a first terminal and a second terminal,

a right resistance-switching device comprising a first terminal and a second terminal, wherein the first terminal of the right resistance-switching device is connected to the first terminal of the left resistance-switching device at an internal node, wherein the second terminal of the left resistance-switching device is directly connected to a word line and the second terminal of the right resistance-switching device is directly connected to a bit line; and

a transistor comprising a source terminal, a drain terminal, and a gate terminal, wherein the drain terminal of the transistor is connected to the left resistance-switching device and the right resistance-switching device at the internal node.

2. The ReRAM according to claim 1 , wherein the left resistance-switching device and the right resistance-switching device are memristors.

3. The ReRAM according to claim 1 , wherein the left resistance-switching device and the right resistance-switching device are in opposite resistance states, wherein resistance states include a high resistance state and alow resistance state.

4. The ReRAM according to claim 1 , wherein the transistor is a minimum sized transistor.

5. The ReRAM according to claim 1 , wherein a logic level of the hybrid memory cell is based on a ratio of resistances of the right resistance-switching device and the left resistance-switching device.

6. The ReRAM according to claim 1 , further comprising:

peripheral circuitry coupled to the hybrid memory cell, the peripheral circuitry configured to program and/or determine a logic level of the hybrid memory cell.

7. The ReRAM according to claim 6 , wherein the peripheral circuitry is configured to determine the logic level by:

applying a read voltage between the second terminal of the left resistance-switching device and the second terminal of the right resistance-switching device;

applying a voltage bias at the gate terminal of the transistor; and

sensing voltage at the internal node via the source of the transistor.

8. The ReRAM according to claim 6 , wherein the peripheral circuitry is configured to program the logic level by:

applying a write voltage between the second terminal of the left resistance-switching device and the second terminal of the right resistance-switching device.

9. The ReRAM according to claim 6 , wherein the peripheral circuitry is configured to program the logic level by:

applying a write voltage between the second terminal of the left resistance-switching device and the second terminal of the right resistance-switching device; and

applying a voltage bias at the gate of the transistor.

10. The ReRAM according to claim 6 , wherein the peripheral circuitry comprises:

a word line driver coupled to the second terminal of the left resistance-switching device via the word line;

an enable line driver coupled to the gate terminal of the transistor;

a bit line driver coupled to the second terminal of the right resistance-switching device via the bit line; and

a sense line driver coupled to the source terminal of the transistor.

11. The ReRAM according to claim 10 , wherein:

the word line driver is configured to provide a first bias to the hybrid memory cell;

the enable line driver is configured to select the hybrid memory cell to program and/or determine the logic level; and

the bit line driver is configured to provide a second bias to the hybrid memory cell.

12. The ReRAM according to claim 1 , wherein the transistor is a p-type transistor or an n-type transistor.

13. A method for programming a hybrid memory cell of a resistive random-access memory (ReRAM), the method comprising:

applying a write voltage between a second terminal of a left resistance-switching device and a second terminal of a right resistance-switching device, wherein a first terminal of the left resistance-switching device is connected to a first terminal of the right resistance-switching device at an internal node; and

removing the write voltage after a predetermined time;

wherein the hybrid memory cell comprises the left resistance-switching device, the right resistance-switching device, and a transistor,

wherein the second terminal of the left resistance-switching device is directly connected to a word line and the second terminal of the right resistance-switching device is directly connected to a bit line.

14. The method according to claim 13 , further comprising:

applying a first voltage bias at a gate of the transistor, wherein a drain of the transistor is connected to the internal node; and

removing the first voltage bias after a second predetermined time.

15. The method according to claim 13 , further comprising:

monitoring the internal node to determine an internal node voltage by applying a first voltage bias at a gate of the transistor; and

determining that the predetermined time is a time that the internal node voltage crosses half of the write voltage.

16. A method for determining a logic level of a hybrid memory cell of a resistive random-access memory (ReRAM), the method comprising:

applying a read voltage between a second terminal of a left resistance-switching device and a second terminal of a right resistance-switching device, wherein a first terminal of the left resistance-switching device is connected to a first terminal of the right resistance-switching device at an internal node;

applying a voltage bias at a gate of a transistor, wherein a drain of the transistor is connected to the internal node; and

sensing voltage at the internal node via a source of the transistor;

wherein the hybrid memory cell comprises the left resistance-switching device, the right resistance-switching device, and the transistor.

17. The method according to claim 16 , further comprising:

comparing the sensed voltage to a threshold voltage;

determining that the logic level of the hybrid memory cell is logic ‘1’ when the sensed voltage is greater than the threshold voltage; and

determining that the logic level of the hybrid memory cell is logic ‘0’ when the sensed voltage is less than the threshold voltage.

18. The method according to claim 17 , wherein the threshold voltage is the read voltage divided by 2.

19. The method according to claim 16 , wherein the logic level of the hybrid memory cell is based on a ratio of resistances of the right resistance-switching device and the left resistance-switching device.

20. The method according to claim 16 , wherein the transistor is a minimum sized transistor.