Hybrid transistor and memory cell
A hybrid switch and memory cell includes a transistor device that has an atomically-thin semiconductor material channel, source/drain electrodes, and gate dielectric. The cell includes a resistive-random-access-memory having a thin conductive edge and a 2D insulator layer over the thin conductive edge, wherein the 2D insulator layer extends over the semiconductor channel and serves as the gate dielectric in the transistor device.
1. A hybrid transistor and memory cell, comprising:
a substrate with a step;
a thin conductive material on the substrate extended to an edge of the step to expose an edge of the thin conductive material;
a gap in the thin conductive material and a 2D semiconductor material formed within the gap connecting thin conductive material sections on either side of the gap;
a source electrode contacting the thin conductive material on an opposite side of the 2D semiconductor material from the edge of the thin conductive material;
a dual function gate dielectric and switching material upon the thin conductive material and the 2D semiconductor material;
a gate dielectric on the dual function dielectric in alignment with the 2D semiconductor material;
a gate electrode on the upper gate dielectric; and
a bit-line electrode on the dual function dielectric and switching material in alignment with the edge of the thin conductive material.
2. The hybrid transistor and memory cell of claim 1 , wherein the thin conductive material comprises van der Waals material.
3. The hybrid transistor and memory cell of claim 2 , wherein the van der Waals material comprises graphene.
4. The hybrid transistor and memory cell of claim 3 , wherein the 2D semiconductor material comprises a transition-metal-dichalcogenide material.
5. The hybrid transistor and memory cell of claim 4 , wherein the 2D semiconductor material comprises tungsten-disulphide (WS 2 ).
6. The hybrid transistor and memory cell of claim 4 , wherein the dual function dielectric and switching material comprises hexagonal-boron nitride (h-BN).
7. A memory array with active transistor functions comprising a plurality of the hybrid transistor and memory cells of claim 1 in an array, wherein individual connections to the memory cells are via source-lines (SL) and bit-lines (BL).
8. The memory array of claim 7 , wherein the SL and BL are formed of one of copper, cobalt, ruthenium, or tungsten or a bilayer thereof.
9. The memory array of claim 7 , wherein the SL and BL are formed of engineered/doped multi-layer graphene interconnects.
10. The hybrid transistor and memory cell of claim 1 , wherein the gate electrode and bit electrode are connected to each other to enable device switching with unidirectional current pulses, i.e., unipolar operation.
11. A hybrid transistor and memory cell, comprising:
a transistor device having a 2D semiconductor material channel;
a resistive-random-access-memory having a thin conductive material conductive edge electrode and a 2D insulator layer over the thin conductive material edge electrode, wherein the 2D insulator layer extends over the channel and serves as dielectric in the transistor device.
12. The hybrid transistor and memory cell of claim 11 , wherein the thin conductive edge electrode comprises one of a van der Waals material, metal and silicide and the 2D-insulator layer comprises hexagonal boron nitride.
13. The hybrid transistor and memory cell of claim 11 , wherein the thin conductive material edge is a monolayer formed over a step on an insulating substrate.
14. A hybrid transistor and memory cell, comprising:
a transistor device and a resistive resistive-random-access-memory access device that share a 2D dielectric that can store electrical energy in its electric field as a dielectric for the transistor device and as an active switching layer for the resistive resistive-random-access-memory access device;
electrodes for the transistor device and the resistive resistive-random-access-memory access device; and
thin conductive material arranged such that a confined conductive filament is created with appropriate voltage application to allow current to flow between electrodes and indicate storage of a data bit “1” and such that application of an appropriate opposite voltage removes the conductive filament to indicate storage of a data bit “0”.
15. A hybrid transistor and memory cell in accordance with claim 14 in a memory array, wherein the memory array is part of a 3D integration (formed via low thermal budget transistor, memory, dielectrics and interconnect material, and their process integration schemes, and is configured as an ultra-high density (both lateral and vertical) stacked 3D integrated circuits.