Memory device and operating method thereof
There are provided a memory device for improving performance by decreasing a time at which a program operation is completed while decreasing a peak current flowing through a bit line, and an operating method of the memory device.
1. A memory device comprising:
a plurality of memory cells;
a plurality of page buffers each coupled to corresponding memory cells through a plurality of bit lines, and configured to temporarily store data to be respectively stored in the plurality of memory cells; and
a page buffer controller configured to control one or more voltages to be applied to the plurality of bit lines in a program operation of storing the data in the plurality of memory cells, wherein
the program operation includes a plurality of program loops, each including a program voltage apply operation and a verify operation,
the program voltage apply operation includes a precharge period, a program voltage apply period, and a discharge period,
the plurality of page buffers are configured to provide a bit line voltage to the plurality of bit lines in response to a page buffer sensing signal output from the page buffer controller, and
the page buffer controller includes:
a first signal provider configured to provide a first pulse signal as the page buffer sensing signal during a first period in the precharge period, the first pulse signal having a first voltage level greater than a ground voltage; and
a second signal provider configured to provide a second pulse signal as the page buffer sensing signal after the first period, the second pulse signal increasing from the first voltage level to a second voltage level with a slope determined according to a loop count of the plurality of program loops, the slope corresponding to one of a plurality of predetermined slopes.
2. The memory device of claim 1 , wherein
when the loop count is equal to or less than a first reference count or when the loop count is greater than a second reference count which is greater than the first reference count, the second signal provider provides the second pulse signal to include a first ramp signal that increases with a first slope greater than a second slope during a second period, the second period occurring after the first period in the precharge period.
3. The memory device of claim 2 , wherein
the second voltage level corresponds to a turn-on voltage at which a page buffer sensing transistor in the page buffer is turned on,
the page buffer sensing transistor connects a bit line and a common sensing node in response to the page buffer sensing signal, and
the second signal provider provides a third pulse signal as the page buffer sensing signal after the second period, the third pulse signal having the second voltage level.
4. The memory device of claim 3 , wherein
while the first ramp signal and the third pulse signal having the second voltage level are supplied, the ground voltage is applied to a word line commonly connected to the plurality of memory cells.
5. The memory device of claim 2 , wherein
when the loop count is greater than the first reference count and equal to or less than the second reference count, the second signal provider provides a second ramp signal as the page buffer sensing signal during a third period, the second ramp signal increasing with the second slope during the third period which is longer than the second period.
6. The memory device of claim 5 , wherein
the second voltage level corresponds to a turn-on voltage at which a page buffer sensing transistor in the page buffer is turned on,
the page buffer sensing transistor connects a bit line and a common sensing node in response to the page buffer sensing signal, and
the second signal provider provides, as the page buffer sensing signal, a third pulse signal having the second voltage level, after the third period.
7. The memory device of claim 5 , wherein
the second voltage level is lower than a turn-on voltage at which a page buffer sensing transistor in the page buffer is turned on,
the page buffer sensing transistor connects a bit line and a common sensing node in response to the page buffer sensing signal, and
the page buffer controller further includes a third signal provider configured to provide, as the page buffer sensing signal, a third pulse signal having the turn-on voltage, after the third period.
8. The memory device of claim 7 , wherein
while the second ramp signal and the third pulse signal having the turn-on voltage are supplied, the ground voltage is applied to a word line commonly connected to the plurality of memory cells.
9. A memory device comprising:
a plurality of memory cells;
a plurality of page buffers each coupled to corresponding memory cells through a plurality of bit lines, and configured to temporarily store data in respective ones of the plurality of memory cells; and
a page buffer controller configured to control one or more voltages to be applied to the plurality of bit lines in a program operation of storing the data in the plurality of memory cells, wherein
the program operation includes a plurality of program loops, each including a program voltage apply operation and a verify operation,
the program voltage apply operation includes a precharge period, a program voltage apply period, and a discharge period,
the plurality of page buffers are configured to provide a bit line voltage to the plurality of bit lines in response to a page buffer sensing signal output from the page buffer controller, and
the page buffer controller includes:
a first signal provider configured to provide a first pulse signal as the page buffer sensing signal during a first period in the precharge period, the first pulse signal having a first voltage level higher than a ground voltage; and
a second signal provider configured to provide a step signal as the page buffer sensing signal after the first period, the step signal increasing from the first voltage level to a second voltage level based on a step voltage, the step voltage corresponding to a loop count of the plurality of program loops among a plurality of predetermined step voltages.
10. The memory device of claim 9 , wherein
when the loop count is equal to or less than a first reference count or when the loop count is greater than a second reference count greater than the first reference count, the second signal provider provides a first step signal as the page buffer sensing signal during a second period, which occurs after the first period in the precharge period, the first step signal increasing based on a first step voltage greater than a second step voltage.
11. The memory device of claim 10 , wherein
when the loop count is greater than the first reference count and is equal to or less than the second reference count, the second signal provider provides a second step signal as the page buffer sensing signal during a third period longer than the second period, the second step signal increasing based on the second step voltage.
12. The memory device of claim 11 , wherein
the second voltage level is lower than a turn-on voltage at which a page buffer sensing transistor in the page buffer is turned on,
the page buffer sensing transistor connects a bit line and a common sensing node in response to the page buffer sensing signal, and
the page buffer controller includes a third signal provider configured to provide a second pulse signal after the third period, the second pulse signal provided after the third period serving as the page buffer sensing signal and having the turn-on voltage.
13. A method for operating a memory device, the method comprising:
providing a first pulse signal to a page buffer during a first period, the first pulse signal serving as a page buffer sensing signal and having a first voltage level higher than a ground voltage;
providing the page buffer with a ramp signal after the first period, the ramp signal serving as the page buffer sensing signal and increasing from the first voltage level to a second voltage level with a slope determined based on a loop count of a plurality of program loops, the slope corresponding to one of a plurality of predetermined slopes;
providing the page buffer with a second pulse signal after the ramp signal reaches the second voltage level, the second pulse signal serving as the page buffer sensing signal and having a third voltage level higher or equal to the second voltage level; and
applying a program voltage to a word line commonly connected to a plurality of memory cells.
14. The method of claim 13 , wherein the providing of the page buffer with the ramp signal as the page buffer sensing signal includes
providing a first ramp signal during a second period in a program loop having a loop count equal to or less than a first reference count or greater than a second reference count which is greater than the first reference count, the first ramp signal increasing with a first slope greater than a second slope and the second period occurring after the first period.
15. The method of claim 14 , wherein
the providing of the page buffer with the second pulse signal includes providing the second pulse signal after the second period, and
the third voltage level is equal to the second voltage level.
16. The method of claim 15 , further comprising
applying the ground voltage to the word line commonly connected to the plurality of memory cells, while the first ramp signal and the second pulse signal are provided.
17. The method of claim 14 , wherein, the providing of the page buffer with the ramp signal as the page buffer sensing signal includes
providing a second ramp signal during a third period longer than the second period in a program loop having a loop count greater than the first reference count and equal to or less than the second reference count, the second ramp signal increasing with the second slope and the third period occurring after the first period.
18. The method of claim 17 , wherein the providing of the second pulse signal having the third voltage level higher than the second voltage level is performed after the third period.
19. The method of claim 18 , further comprising
applying the ground voltage to the word line commonly connected to the plurality of memory cells, while the second ramp signal and the second pulse signal are supplied.
20. A memory device comprising:
a plurality of memory cells;
a voltage generator configured to generate operating voltages for a program operation of storing data in the plurality of memory cells;
a plurality of page buffers respectively connected to the plurality of memory cells through a plurality of bit lines, the plurality of page buffers providing a bit line voltage to the plurality of bit lines in response to a page buffer sensing signal; and
a page buffer controller configured to provide the page buffer sensing signals to the plurality of page buffers in the program operation, wherein the page buffer controller includes:
a first signal provider configured to provide a pulse signal as the page buffer sensing signal during a first period, the pulse signal generated by the voltage generator; and
a second signal provider configured to provide a ramp signal as the page buffer sensing signal during a second period after the first period, the ramp signal having a slope determined based on a loop count of a program loop which represents a degree to which the program operation is performed, and
the second signal provider including
a plurality of switches provided with a page buffer pump voltage;
a plurality of transistors grouped and connected in series to the plurality of switches, the plurality of transistors configured to output a bias current from the plurality of switches in response to a voltage control signal, the voltage control signal provided based on the loop count of the program loop;
a capacitor commonly connected to the plurality of transistors and configured to charge a capacitor voltage with respect to the bias current; and
a voltage output circuit commonly connected to the plurality of transistors and configured to transfer a capacitor voltage corresponding to the page buffer sensing signal.