Granted Patent B2

US 12,394,487 · App. 18/464,383 · Granted Aug 19, 2025

Inventor: Hyun Seo (Suwon-si, KR)

Assignee: Samsung Electronics Co., Ltd.

G11C16/10G11C16/0483G11C16/08G11C16/24G11C16/32

Abstract

Claims (81)

1. A method of programming data in a nonvolatile memory device including a plurality of memory cells and a page buffer configured to control the plurality of memory cells, wherein the plurality of memory cells are electrically connected to a plurality of wordlines and a plurality of bitlines, the method comprising:

in a first program time period of a first program loop, applying a program voltage having a first program voltage to a selected wordline that is electrically connected to a target memory cell on which a program operation is performed; and

in the first program time period, applying a bitline shut-off signal having a first delay to the page buffer,

wherein the program voltage is applied to the selected wordline multiple times during one program loop while a magnitude of the program voltage is changed for each of the multiple times that the program voltage is applied,

wherein, as the magnitude of the program voltage increases, a delay of the bitline shut-off signal increases, and

wherein the delay of the bitline shut-off signal corresponds to a time period during which the bitline shut-off signal maintains a ground voltage.

2. The method of claim 1 , further comprising:

in a second program time period of the first program loop after the first program time period of the first program loop, applying the program voltage having a second program voltage different from the first program voltage to the selected wordline; and

in the second program time period, applying the bitline shut-off signal having a second delay different from the first delay to the page buffer.

3. The method of claim 2 ,

wherein the second program voltage is higher than the first program voltage, and

wherein the second delay is longer than the first delay.

4. The method of claim 2 ,

wherein the second program voltage is lower than the first program voltage, and

wherein the second delay is shorter than the first delay.

5. The method of claim 1 , further comprising:

in a third program time period of a second program loop after the first program loop, applying the program voltage having a third program voltage higher than the first program voltage to the selected wordline; and

in the third program time period, applying the bitline shut-off signal having a third delay longer than the first delay to the page buffer.

6. The method of claim 1 ,

wherein, as the magnitude of the program voltage increases, the delay of the bitline shut-off signal increases, and a slope of the bitline shut-off signal increases, and

wherein the slope of the bitline shut-off signal corresponds to an increase from the ground voltage to a bitline forcing voltage.

7. The method of claim 6 ,

wherein the bitline shut-off signal has a plurality of step waveforms and increases from the ground voltage to the bitline forcing voltage,

wherein the slope of the bitline shut-off signal is based on adjusting at least one of a cycle and a step difference,

wherein the cycle corresponds to a time period during which each of the plurality of step waveforms has a fixed voltage, and

wherein the step difference corresponds to a difference between voltages of adjacent step waveforms.

8. The method of claim 1 ,

wherein the nonvolatile memory device further includes:

a plurality of string selection transistors electrically connected to a plurality of string selection lines and electrically connected to some of the plurality of memory cells,

wherein the method further comprises:

in the first program time period, applying a string selection voltage having a first string selection voltage to a selected string selection line that is electrically connected to a target string selection transistor and electrically connected to the target memory cell, and

wherein, as the magnitude of the program voltage increases, the string selection voltage increases.

9. The method of claim 8 , further comprising:

in a second program time period of the first program loop after the first program time period of the first program loop, applying the program voltage having a second program voltage different from the first program voltage to the selected wordline;

in the second program time period, applying the bitline shut-off signal having a second delay different from the first delay to the page buffer; and

in the second program time period, applying the string selection voltage having a second string selection voltage different from the first string selection voltage to the selected string selection line.

10. The method of claim 8 , further comprising:

in a third program time period of a second program loop after the first program loop, applying the program voltage having a third program voltage higher than the first program voltage to the selected wordline;

in the third program time period, applying the bitline shut-off signal having a third delay longer than the first delay to the page buffer; and

in the third program time period, applying the string selection voltage having a third string selection voltage higher than the first string selection voltage to the selected string selection line.

11. The method of claim 1 ,

wherein the plurality of memory cells are in a vertical direction on a substrate, and

wherein the program operation is sequentially performed from an uppermost memory cell farthest from the substrate of the plurality of memory cells to a lowermost memory cell closest to the substrate of the plurality of memory cells.

12. The method of claim 11 ,

wherein the nonvolatile memory device further includes:

a plurality of ground selection transistors electrically connected to a plurality of ground selection lines and a common source line and electrically connected to some of the plurality of memory cells, and further comprising:

controlling the delay of the bitline shut-off signal starting from a P-th program loop among a plurality of program loops performed on the target memory cell, where P is a natural number, and

wherein, while an initial precharge operation is performed in the P-th program loop, a magnitude of a ground selection voltage applied to a selected ground selection line that is electrically connected to a target ground selection transistor and electrically connected to the target memory cell, or a magnitude of a common source voltage applied to the common source line is changed.

13. The method of claim 11 , wherein, as a distance between the target memory cell and the substrate decreases, the delay of the bitline shut-off signal increases while the program operation is performed.

14. The method of claim 1 ,

wherein the plurality of memory cells are in a vertical direction on a substrate, and

wherein the program operation is sequentially performed from a lowermost memory cell closest to the substrate of the plurality of memory cells to an uppermost memory cell farthest from the substrate of the plurality of memory cells.

15. The method of claim 14 , further comprising:

controlling the delay of the bitline shut-off signal starting from a Q-th program loop among a plurality of program loops performed on the target memory cell, where Q is a natural number, and

wherein, in the Q-th program loop, a timing of performing an initial precharge operation and a timing of performing a bitline setup operation are different from each other.

16. The method of claim 14 , wherein, as a distance between the target memory cell and the substrate increases, the delay of the bitline shut-off signal increases while the program operation is performed.

17. The method of claim 1 , wherein, as an operating temperature of the nonvolatile memory device increases, the delay of the bitline shut-off signal increases while the program operation is performed.

18. A nonvolatile memory device comprising:

a memory cell array including a plurality of memory cells electrically connected to a plurality of wordlines and a plurality of bitlines;

a page buffer circuit including a page buffer configured to control the plurality of memory cells; and

a control circuit configured to apply a program voltage having a first program voltage to a selected wordline that is electrically connected to a target memory cell on which a program operation is performed in a first program time period of a first program loop, and configured to apply a bitline shut-off signal having a first delay to the page buffer in the first program time period,

wherein the control circuit is configured to apply the program voltage to the selected wordline multiple times during one program loop while a magnitude of the program voltage is changed for each of the multiple times that the program voltage is applied,

wherein, as the magnitude of the program voltage increases, a delay of the bitline shut-off signal increases, and

wherein the delay of the bitline shut-off signal corresponds to a time period during which the bitline shut-off signal maintains a ground voltage.

19. The nonvolatile memory device of claim 18 , wherein the page buffer includes:

a bitline selection circuit configured to be selectively electrically connected to a selected bitline that is electrically connected to the target memory cell based on the bitline shut-off signal;

a sensing latch configured to store bitline setup information received by the selected bitline; and

a forcing latch configured to store bitline forcing information received by the selected bitline.

20. A method of programming data in a nonvolatile memory device including a plurality of memory cells and a page buffer configured to control the plurality of memory cells, wherein the plurality of memory cells are electrically connected to a plurality of wordlines and a plurality of bitlines, the method comprising:

in a first program time period of a first program loop, applying a program voltage having a first program voltage to a selected wordline that is electrically connected to a target memory cell on which a program operation is performed;

in the first program time period, applying a bitline shut-off signal having a first delay to the page buffer;

in a second program time period of the first program loop after the first program time period of the first program loop, applying the program voltage having a second program voltage different from the first program voltage to the selected wordline;

in the second program time period, applying the bitline shut-off signal having a second delay different from the first delay to the page buffer;

in a third program time period of a second program loop after the first program loop, applying the program voltage having a third program voltage higher than the first program voltage to the selected wordline; and

in the third program time period, applying the bitline shut-off signal having a third delay longer than the first delay to the page buffer,

wherein the program voltage is applied to the selected wordline multiple times during one program loop while a magnitude of the program voltage is changed for each of the multiple times that the program voltage is applied,

wherein, as the magnitude of the program voltage increases, a delay of the bitline shut-off signal increases, and a slope of the bitline shut-off signal increases,

wherein the delay of the bitline shut-off signal corresponds to a time period during which the bitline shut-off signal maintains a ground voltage,

wherein the slope of the bitline shut-off signal corresponds to an increase from the ground voltage to a bitline forcing voltage,

wherein, in response to the second program voltage being higher than the first program voltage, the second delay is longer than the first delay, and

wherein, in response to the second program voltage being lower than the first program voltage, the second delay is shorter than the first delay.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (21)