Interconnect structure and electronic apparatus including the same

1. An interconnect structure comprising:

a conductive layer;

a dielectric layer surrounding at least a part of the conductive layer; and

a diffusion barrier layer between the conductive layer and the dielectric layer, the diffusion barrier layer configured to limit a conductive material of the conductive layer from diffusing into the dielectric layer,

at least one of the dielectric layer and the diffusion barrier layer including at least one of an amorphous boron nitride layer and a nanocrystalline boron nitride layer, wherein

at least one of the dielectric layer and the diffusion barrier layer has a hydrogen content of about 10% or less and greater than 0%,

the amorphous boron nitride layer includes one or more crystals having a size of about 3 nm or less, and

the nanocrystalline boron nitride layer includes one or more crystals having a size of about 0.5 nm to about 100 nm.

2. The interconnect structure of claim 1 , wherein

the diffusion barrier layer comprises at least one of the amorphous boron nitride layer and the nanocrystalline boron nitride layer, and

the dielectric layer comprises a different dielectric material from a material of the diffusion barrier layer.

3. The interconnect structure of claim 1 , wherein the dielectric layer and the diffusion barrier layer each comprise at least one of the amorphous boron nitride layer and the nanocrystalline boron nitride layer.

4. The interconnect structure of claim 3 , wherein the dielectric layer and the diffusion barrier layer are integrated with each other.

5. The interconnect structure of claim 1 , wherein

the dielectric layer comprises at least one of the amorphous boron nitride layer and the nanocrystalline boron nitride layer, and

the diffusion barrier layer comprises a metal other than boron.

6. The interconnect structure of claim 1 , wherein a thickness of the diffusion barrier layer is about 5 nm or less.

7. The interconnect structure of claim 1 , wherein a thickness of the dielectric layer is about 5 nm or more.

8. The interconnect structure of claim 1 , wherein at least one of the dielectric layer and the diffusion barrier layer has a dielectric constant of about 2.5 or less at an operating frequency of 100 kHz.

9. The interconnect structure of claim 1 , wherein at least one of the dielectric layer and the diffusion barrier layer has a ratio of boron to nitrogen of about 0.9 to about 1.1.

10. The interconnect structure of claim 1 , wherein at least one of the dielectric layer and the diffusion barrier layer is non-porous.

11. The interconnect structure of claim 1 , wherein at least one of the dielectric layer and the diffusion barrier layer comprises at least one pore.

12. The interconnect structure of claim 1 , wherein at least one of the dielectric layer and the diffusion barrier layer has a mass density of about 1 to about 3 g/cm 3 .

13. The interconnect structure of claim 1 , wherein a breakdown field of at least one of the dielectric layer and the diffusion barrier layer is about 4 MV-cm −1 or more.

14. The interconnect structure of claim 1 , wherein at least one of the dielectric layer and the diffusion barrier layer has about 0.3 to about 0.6 root-mean-square (RMS) roughness value.

15. The interconnect structure of claim 1 , wherein

the dielectric layer comprises a first dielectric layer comprising a trench of a first depth,

the diffusion barrier layer comprises a first diffusion barrier layer on an inner wall of the trench, and

the conductive layer comprises a first conductive layer filling an inside of the trench.

16. The interconnect structure of claim 1 , wherein

the dielectric layer comprises a second dielectric layer comprising a via hole,

the diffusion barrier layer comprises a second diffusion barrier layer disposed on an inner wall of the via hole, and

the conductive layer comprises a second conductive layer filling an inside of the via hole.

17. The interconnect structure of claim 16 , wherein the via hole is stepped.

18. An electronic apparatus comprising:

a device layer comprising at least one of a transistor, a capacitor, and a resistor; and

the interconnect structure of claim 1 connected to the device layer.

19. The electronic apparatus of claim 18 , wherein the device layer comprises at least one of a memory device, a display device, and an integrated circuit device.

20. An interconnect structure comprising:

a conductive layer; and

a boron nitride structure surrounding at least part of the conductive layer,

the boron nitride structure including at least one of an amorphous boron nitride layer and a nanocrystalline boron nitride layer, and

the boron nitride structure configured to limit a conductive material of the conductive layer from diffusing through at least a portion of the boron nitride structure, wherein

at least one of the amorphous boron nitride layer and the nanocrystalline boron nitride layer has a hydrogen content of about 10% or less,

the amorphous boron nitride layer includes one or more crystals having a size of about 3 nm or less, and

the nanocrystalline boron nitride layer includes one or more crystals having a size of about 0.5 nm to about 100 nm.

21. The interconnect structure of claim 1 , further comprising:

a substrate, wherein

the conductive layer is on the substrate,

the diffusion barrier layer includes the amorphous boron nitride layer, the nanocrystalline boron nitride layer, or both the amorphous boron nitride layer and the nanocrystalline boron nitride layer, and

the diffusion barrier layer covers at least one of a bottom of the conductive layer and an upper surface of the conductive layer.