Semiconductor device and method of fabricating the same

1. A semiconductor device comprising:

a plurality of lower electrodes arranged on a semiconductor substrate in a honeycomb structure; and

a support connected to the plurality of lower electrodes and defining a plurality of open areas through which the plurality of lower electrodes are exposed,

wherein a center point of each of the plurality of open areas is arranged at a center point of a triangle formed by center points of three corresponding neighboring lower electrodes among the plurality of lower electrodes.

2. The semiconductor device of claim 1 , wherein a first hexagon is formed by lower electrodes positioned at vertexes of six neighboring lower electrodes and a lower electrode positioned at a center point of the first hexagon,

wherein each of the six neighboring lower electrodes is positioned at a center point of a corresponding one of six hexagons formed by the plurality of lower electrodes, and

wherein each of the six hexagons formed by the plurality of lower electrodes comprises the lower electrode positioned at the center point of the first hexagon.

3. The semiconductor device of claim 2 , wherein the plurality of open areas are arranged in a honeycomb structure,

wherein a second hexagon is formed by open areas positioned at vertexes of six neighboring open areas and an open area is positioned at a center point of the second hexagon,

wherein each of the six neighboring open areas is positioned at a center point of a corresponding one of six hexagons formed by the plurality of open areas, and

wherein each of the six hexagons formed by the plurality of open areas comprises the open area positioned at the center point of the second hexagon.

4. The semiconductor device of claim 3 , wherein the first hexagon occupies a first area,

wherein the second hexagon occupies a second area, and

wherein the first area is substantially equal to the second area.

5. The semiconductor device of claim 1 , wherein three segments of one of the plurality of lower electrodes are exposed by three open areas from among the plurality of open areas in different directions.

6. The semiconductor device of claim 1 , wherein, three lower electrodes are provided within one of the plurality of open areas.

7. The semiconductor device of claim 1 , wherein the plurality of lower electrodes are formed with a first pitch,

wherein the plurality of open areas are formed with a second pitch, and

wherein the first pitch is substantially equal to the second pitch.

8. The semiconductor device of claim 7 , wherein the plurality of lower electrodes are arranged in a first direction with the first pitch and are arranged in a second direction intersecting the first direction with a third pitch that is half of the first pitch.

9. The semiconductor device of claim 8 , wherein, when a distance between center points of two neighboring lower electrodes among the plurality of lower electrodes is 3.0 minimum lithographic feature sizes (F),

wherein a distance between center points of two neighboring open areas is about 3.0 F in the first direction and is about 2.6 F in the second direction.

10. The semiconductor device of claim 1 , wherein a ratio between a number of lower electrodes and a number of open areas in a unit area is 1:1.

11. A semiconductor device comprising:

a plurality of lower electrodes provided on an upper surface of a semiconductor substrate and arranged in a first direction and a second direction intersecting each other, wherein the first direction and the second direction are parallel to the upper surface; and

a support connected to the plurality of lower electrodes and defining a plurality of open areas,

wherein a support pattern is repeatedly formed in the support, and

wherein three segments of each of the plurality of lower electrodes are exposed by the plurality of open areas.

12. The semiconductor device of claim 11 , wherein the plurality of lower electrodes are formed with a first pitch,

wherein the plurality of open areas are formed with a second pitch by an extreme ultraviolet (EUV) process, and

wherein the first pitch is substantially equal to the second pitch.

13. The semiconductor device of claim 12 , wherein a first diameter of each of the plurality of lower electrodes is substantially equal to a second diameter of each of the plurality of open areas.

14. The semiconductor device of claim 11 , wherein the support pattern comprises three side surfaces which contact the plurality of lower electrodes and three side surfaces exposed to the plurality of open areas, and

wherein the three side surfaces which contact the plurality of lower electrodes and the three side surfaces exposed to the plurality of open areas are alternately arranged in a clockwise direction.

15. The semiconductor device of claim 11 , wherein the support pattern is repeatedly arranged in a honeycomb structure,

wherein a hexagon is formed by support patterns positioned at vertexes of six neighboring support patterns and a support pattern positioned at a center point of the hexagon,

wherein each of the six neighboring support patterns is positioned at a center point of a corresponding one of six hexagons formed by the six neighboring support patterns, and

wherein each of the six hexagons formed by the six neighboring support patterns comprises the support pattern positioned at a center point of the hexagon.

16. A semiconductor device comprising:

a plurality of first conductive lines, wherein the plurality of first conductive lines are spaced apart from one another in a first direction and a second direction, the first direction and the second direction being parallel with an upper surface of a semiconductor substrate and the second direction intersecting with the first direction;

channel layers arranged in a matrix on the plurality of first conductive lines and spaced apart from one another in the first direction and the second direction;

gate electrodes disposed on both side walls of each of the channel layers that extend in the first direction;

gate insulating layers surrounding side walls of the channel layers and arranged between the channel layers and the gate electrodes;

a plurality of capacitors arranged on the channel layers, each of which comprises a lower electrode, a dielectric layer, and an upper electrode; and

a support connected to the plurality of lower electrodes and defining a plurality of open areas through which the plurality of lower electrodes are exposed,

wherein a center point of each of the plurality of open areas is arranged at a center point of a triangle formed by center points of three corresponding neighboring lower electrodes among the plurality of lower electrodes.

17. The semiconductor device of claim 16 , further comprising:

contact plugs arranged on the channel layers;

an interlayer insulating layer surrounding side walls of the contact plugs; and

an etch stop pattern arranged on the interlayer insulating layer,

wherein the plurality of capacitors are arranged on the contact plugs.

18. The semiconductor device of claim 16 , wherein the plurality of lower electrodes and the plurality of open areas are both arranged in a honeycomb structure.

19. The semiconductor device of claim 16 , wherein the plurality of lower electrodes are formed with a first pitch by an extreme ultraviolet (EUV) process,

wherein the plurality of open areas are formed with a second pitch by an EUV process, and

wherein the first pitch is substantially equal to the second pitch.

20. The semiconductor device of claim 19 , wherein the plurality of lower electrodes are arranged with the first pitch in the first direction and are arranged in the second direction with a third pitch that is half of the first pitch.