Insulation layer arrangement for magnetic tunnel junction device

1. A method of manufacturing a semiconductor device, the method comprising:

providing a substrate including a cell region and a peripheral region;

forming a lower insulation layer on the substrate, the lower insulation layer including a first portion on the cell region and a second portion on the peripheral region;

forming magnetic tunnel junction patterns on the first portion of the lower insulation layer;

forming a capping insulation layer covering the magnetic tunnel junction patterns, the capping insulation layer including a first portion on the cell region and a second portion on the peripheral region; and

performing an etch-back process on an entire surface of the capping insulation layer to reduce a thickness of the capping insulation layer across the entire surface of the capping insulation layer and to remove the second portion of the capping insulation layer,

wherein the second portion of the lower insulation layer is exposed by the etch-back process.

2. The method of claim 1 , wherein the first portion of the capping insulation layer is partially removed by the etch-back process.

3. The method of claim 2 , wherein, after the etch-back process is performed, the first portion of the capping insulation layer partially remains in a gap between the magnetic tunnel junction patterns.

4. The method of claim 3 , wherein a top surface of the first portion of the capping insulation layer remaining in the gap is positioned higher than top surfaces of the magnetic tunnel junction patterns.

5. The method of claim 1 , wherein forming the magnetic tunnel junction patterns comprises:

forming a magnetic tunnel junction layer on the lower insulation layer;

forming conductive mask patterns on the magnetic tunnel junction layer on the cell region; and

patterning the magnetic tunnel junction layer using the conductive mask patterns as an etch mask.

6. The method of claim 5 , wherein, after the magnetic tunnel junction layer is patterned, a top surface of the second portion of the lower insulation layer is disposed lower than a top surface of the first portion of the lower insulation layer.

7. The method of claim 5 , wherein, after the magnetic tunnel junction layer is patterned, a top surface of the first portion of the lower insulation layer becomes concave between magnetic tunnel junction patterns and a top surface of the second portion of the lower insulation layer becomes flat.

8. The method of claim 1 , further comprising removing the second portion of the lower insulation layer to expose the substrate in the peripheral region.

9. The method of claim 1 , further comprising forming an upper insulation layer covering the first portion of the capping insulation layer after performing the etch-back process,

wherein the upper insulation layer includes a first portion on the cell region and a second portion on the peripheral region.

10. The method of claim 9 , further comprising removing an upper portion of the first portion of the upper insulation layer.

11. A method of manufacturing a semiconductor device, the method comprising:

providing a substrate including a cell region and a peripheral region;

forming a lower insulation layer on the substrate, the lower insulation layer including a first portion on the cell region and a second portion on the peripheral region;

forming magnetic tunnel junction patterns on the first portion of the lower insulation layer and partially etching the first portion and the second portion of the lower insulation layer;

forming a capping insulation layer covering the magnetic tunnel junction patterns to be in contact with the lower insulation layer, the capping insulation layer including a first portion on the cell region and a second portion on the peripheral region; and

performing an etch-back process on an entire surface of the capping insulation layer to reduce a thickness of the capping insulation layer across the entire surface of the capping insulation layer and to remove the second portion of the capping insulation layer,

wherein a lower part of the first portion of the capping insulation layer remains between the magnetic tunnel junction patterns after the etch-back process.

12. The method of claim 11 , wherein the second portion of the lower insulation layer is exposed by the etch-back process.

13. The method of claim 11 , wherein, after partially etching the first portion and the second portion of the lower insulation layer, a top surface of the first portion of the lower insulation layer becomes concave between magnetic tunnel junction patterns and a top surface of the second portion of the lower insulation layer becomes flat.

14. The method of claim 11 , wherein, after partially etching the first portion and the second portion of the lower insulation layer, the first portion of the lower insulation layer has a first thickness and the second portion of the lower insulation layer has a second thickness, wherein the first thickness is greater than the second thickness.

15. The method of claim 11 , wherein forming the magnetic tunnel junction patterns comprises:

forming a magnetic tunnel junction layer on the lower insulation layer;

forming conductive mask patterns on the magnetic tunnel junction layer on the cell region; and

patterning the magnetic tunnel junction layer using the conductive mask patterns as an etch mask,

wherein the conductive mask patterns remain on the magnetic tunnel junction patterns, respectively, and

wherein the first portion of the capping insulation layer exposes an upper sidewall of the conductive mask patterns after performing the etch-back process.

16. The method of claim 11 , further comprising:

forming an upper insulation layer covering the first portion of the capping insulation layer after performing the etch-back process;

planarizing the upper insulation layer to remove a portion of the upper insulation layer on the cell region,

wherein the upper insulation layer has a first thickness on the cell region and a second thickness on the peripheral region, the first thickness smaller than the second thickness.

17. A method of manufacturing a semiconductor device, the method comprising:

providing a substrate including a cell region and a peripheral region;

forming a lower insulation layer on the substrate, the lower insulation layer including a first portion on the cell region and a second portion on the peripheral region;

forming a magnetic tunnel junction layer on the lower insulation layer;

forming conductive mask patterns on the magnetic tunnel junction layer on the cell region;

patterning the magnetic tunnel junction layer using the conductive mask patterns as an etch mask to form magnetic tunnel junction patterns on the first portion of the lower insulation layer;

forming a capping insulation layer covering conductive mask patterns and the magnetic tunnel junction patterns to be in contact with the lower insulation layer, the capping insulation layer including a first portion on the cell region and a second portion on the peripheral region; and

performing an etch-back process on an entire surface of the capping insulation layer to reduce a thickness of the capping insulation layer across the entire surface of the capping insulation layer and to remove the second portion of the capping insulation layer, wherein the first portion of the capping insulation layer exposes an upper sidewall of the conductive mask patterns after performing the etch-back process.

18. The method of claim 17 , wherein the patterning of the magnetic tunnel junction layer partially etches the first portion and the second portion of the lower insulation layer, thereby forming a top surface of the first portion of the lower insulation layer to be concave between magnetic tunnel junction patterns and forming a top surface of the second portion of the lower insulation layer to be flat.

19. The method of claim 17 , wherein, after patterning the magnetic tunnel junction layer, the first portion of the lower insulation layer has a first thickness and the second portion of the lower insulation layer has a second thickness, wherein the first thickness is greater than the second thickness.

20. The method of claim 17 , further comprising:

forming an upper insulation layer covering the first portion of the capping insulation layer after performing the etch-back process;

planarizing the upper insulation layer to remove a portion of the upper insulation layer on the cell region,

wherein the upper insulation layer has a first thickness on the cell region and a second thickness on the peripheral region, the first thickness smaller than the second thickness.